| /linux-3.3/arch/arm/mach-omap2/ |
| D | clkt_clksel.c | 2 * clkt_clksel.c - OMAP2/3/4 clksel clock functions
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
24 * clock code for each new chip, since it can be exported from the SoC
47 #include <plat/clock.h>
49 #include "clock.h"
54 * _get_clksel_by_parent() - return clksel struct for a given clk & parent
58 * Scan the struct clksel array associated with the clock to find
59 * the element associated with the supplied parent clock address.
[all …]
|
| D | clock_common_data.c | 2 * linux/arch/arm/mach-omap2/clock_common_data.c
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2009 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
15 * This file contains clock data that is common to both the OMAP2xxx and
16 * OMAP3xxx clock definition files.
19 #include "clock.h"
23 { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_3XXX },
24 { .div = 0 }
28 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX },
[all …]
|
| D | clock3xxx_data.c | 2 * OMAP3 clock data
4 * Copyright (C) 2007-2010 Texas Instruments, Inc.
5 * Copyright (C) 2007-2011 Nokia Corporation
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
25 #include "clock.h"
32 #include "cm-regbits-34xx.h"
34 #include "prm-regbits-34xx.h"
49 * DPLL1 supplies clock to the MPU.
50 * DPLL2 supplies clock to the IVA2.
[all …]
|
| D | clock2420_data.c | 2 * OMAP2420 clock data
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
22 #include "clock.h"
27 #include "prm-regbits-24xx.h"
28 #include "cm-regbits-24xx.h"
35 * 2420 clock tree.
44 * Things are broadly separated below by clock domains. It is
45 * noteworthy that most peripherals have dependencies on multiple clock
[all …]
|
| D | clkt2xxx_sys.c | 2 * OMAP2xxx sys_clk-specific clock code
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
25 #include <plat/clock.h>
27 #include "clock.h"
30 #include "prm-regbits-24xx.h"
36 u32 div; in omap2xxx_get_sysclkdiv() local
38 div = __raw_readl(prcm_clksrc_ctrl); in omap2xxx_get_sysclkdiv()
39 div &= OMAP_SYSCLKDIV_MASK; in omap2xxx_get_sysclkdiv()
[all …]
|
| D | clock2430_data.c | 2 * OMAP2430 clock data
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
22 #include "clock.h"
27 #include "prm-regbits-24xx.h"
28 #include "cm-regbits-24xx.h"
35 * 2430 clock tree.
44 * Things are broadly separated below by clock domains. It is
45 * noteworthy that most peripherals have dependencies on multiple clock
[all …]
|
| /linux-3.3/drivers/mmc/host/ |
| D | sdhci-cns3xxx.c | 20 #include "sdhci-pltfm.h"
27 static void sdhci_cns3xxx_set_clock(struct sdhci_host *host, unsigned int clock) in sdhci_cns3xxx_set_clock() argument
29 struct device *dev = mmc_dev(host->mmc); in sdhci_cns3xxx_set_clock()
30 int div = 1; in sdhci_cns3xxx_set_clock() local
34 if (clock == host->clock) in sdhci_cns3xxx_set_clock()
39 if (clock == 0) in sdhci_cns3xxx_set_clock()
42 while (host->max_clk / div > clock) { in sdhci_cns3xxx_set_clock()
47 if (div < 4) in sdhci_cns3xxx_set_clock()
48 div += 1; in sdhci_cns3xxx_set_clock()
49 else if (div < 256) in sdhci_cns3xxx_set_clock()
[all …]
|
| D | sdhci-esdhc.h | 36 /* pltfm-specific */
39 /* OF-specific */
45 static inline void esdhc_set_clock(struct sdhci_host *host, unsigned int clock) in esdhc_set_clock() argument
48 int div = 1; in esdhc_set_clock() local
56 if (clock == 0) in esdhc_set_clock()
59 while (host->max_clk / pre_div / 16 > clock && pre_div < 256) in esdhc_set_clock()
62 while (host->max_clk / pre_div / div > clock && div < 16) in esdhc_set_clock()
63 div++; in esdhc_set_clock()
65 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", in esdhc_set_clock()
66 clock, host->max_clk / pre_div / div); in esdhc_set_clock()
[all …]
|
| /linux-3.3/arch/arm/mach-tegra/ |
| D | clock.c | 34 #include "clock.h"
41 * To avoid AB-BA locking problems, locks must always be traversed from child
42 * clock to parent clock. For example, when enabling a clock, the clock's lock
44 * parent clock's lock. There is one exceptions to this ordering: When dumping
45 * the clock tree through debugfs. In this case, clk_lock_all is called,
47 * clock lock. If any call to spin_trylock fails, all locked clocks are
49 * the only clock operation that can be called is clk_get_rate_all_locked.
51 * Within a single clock, no clock operation can call another clock operation
53 * clock operation can call any other clock operation on any of it's possible
59 * The clock operations must lock internally to protect against
[all …]
|
| /linux-3.3/arch/arm/plat-s3c24xx/ |
| D | clock-dclk.c | 1 /* linux/arch/arm/plat-s3c24xx/clock-dclk.c
3 * Copyright (c) 2004-2008 Simtec Electronics
11 * S3C24XX - definitions for DCLK and CLKOUT registers
19 #include <mach/regs-clock.h>
20 #include <mach/regs-gpio.h>
22 #include <plat/clock.h>
32 dclkcon |= clk->ctrlbit; in s3c24xx_dclk_enable()
34 dclkcon &= ~clk->ctrlbit; in s3c24xx_dclk_enable()
51 return -EINVAL; in s3c24xx_dclk_setparent()
53 clk->parent = parent; in s3c24xx_dclk_setparent()
[all …]
|
| D | s3c2443-clock.c | 1 /* linux/arch/arm/plat-s3c24xx/s3c2443-clock.c
6 * S3C2443 Clock control suport - common code
13 #include <mach/regs-s3c2443-clock.h>
16 #include <plat/clock.h>
17 #include <plat/clock-clksrc.h>
20 #include <plat/cpu-freq.h>
25 u32 ctrlbit = clk->ctrlbit; in s3c2443_gate()
81 * this is sourced from either the EPLL or the EPLLref clock
103 unsigned long parent_rate = clk_get_rate(clk->parent); in s3c2443_getrate_mdivclk()
104 unsigned long div = __raw_readl(S3C2443_CLKDIV0); in s3c2443_getrate_mdivclk() local
[all …]
|
| /linux-3.3/arch/arm/mach-mxs/ |
| D | clock-mx28.c | 2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
32 #include <mach/clock.h>
35 #include "regs-clkctrl-mx28.h"
52 * DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1
53 * clock pins selected for SAIF1 input clocks.
54 * CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and
55 * SAIF0 clock inputs selected for SAIF1 input clocks.
56 * EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input
58 * EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input
[all …]
|
| D | clock-mx23.c | 2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
31 #include <mach/clock.h>
33 #include "regs-clkctrl-mx23.h"
44 if (clk->enable_reg) { in _raw_clk_enable()
45 reg = __raw_readl(clk->enable_reg); in _raw_clk_enable()
46 reg &= ~(1 << clk->enable_shift); in _raw_clk_enable()
47 __raw_writel(reg, clk->enable_reg); in _raw_clk_enable()
57 if (clk->enable_reg) { in _raw_clk_disable()
58 reg = __raw_readl(clk->enable_reg); in _raw_clk_disable()
[all …]
|
| /linux-3.3/arch/arm/mach-lpc32xx/ |
| D | clock.c | 2 * arch/arm/mach-lpc32xx/clock.c
20 * LPC32xx clock management driver overview
26 * clocks are already running. Stopping a system clock during normal
30 * The LPC32xx high level clock tree looks as follows. Clocks marked with
33 * with a caret are always on if it is the selected clock for the SYSCLK
34 * source. The clock that isn't used for SYSCLK can be enabled and
52 * generate various clock rates up to 266MHz and beyond. The internal bus
57 * dividers as part of the IP itself. Because of this, the system clock
70 * complexities of clock management during clock frequency changes,
71 * there are some limitations to the clock driver explained below:
[all …]
|
| /linux-3.3/sound/aoa/soundbus/i2sbus/ |
| D | interface.h | 2 * i2sbus driver -- interface register definitions
62 * - clock source
63 * - MClk divisor
64 * - SClk divisor
65 * - SClk master flag
66 * - serial format (sony, i2s 64x, i2s 32x, dav, silabs)
67 * - external sample frequency interrupt (don't understand)
68 * - external sample frequency
71 /* clock source. You get either 18.432, 45.1584 or 49.1520 MHz */
77 /* also, let's define the exact clock speeds here, in Hz */
[all …]
|
| /linux-3.3/arch/arm/mach-s3c2412/ |
| D | clock.c | 1 /* linux/arch/arm/mach-s3c2412/clock.c
6 * S3C2412,S3C2413 Clock control support
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
40 #include <plat/regs-serial.h>
41 #include <mach/regs-clock.h>
42 #include <mach/regs-gpio.h>
45 #include <plat/clock.h>
59 unsigned int clocks = clk->ctrlbit; in s3c2412_clkcon_enable()
94 /* clock selections */
113 return -EINVAL; in s3c2412_setparent_usysclk()
[all …]
|
| /linux-3.3/arch/arm/plat-spear/ |
| D | clock.c | 2 * arch/arm/plat-spear/clock.c
4 * Clock framework for SPEAr platform
22 #include <plat/clock.h>
39 if (!clk->en_reg) in generic_clk_enable()
40 return -EFAULT; in generic_clk_enable()
42 val = readl(clk->en_reg); in generic_clk_enable()
43 if (unlikely(clk->flags & RESET_TO_ENABLE)) in generic_clk_enable()
44 val &= ~(1 << clk->en_reg_bit); in generic_clk_enable()
46 val |= 1 << clk->en_reg_bit; in generic_clk_enable()
48 writel(val, clk->en_reg); in generic_clk_enable()
[all …]
|
| /linux-3.3/arch/arm/plat-samsung/ |
| D | clock-clksrc.c | 1 /* linux/arch/arm/plat-samsung/clock-clksrc.c
22 #include <plat/clock.h>
23 #include <plat/clock-clksrc.h>
24 #include <plat/cpu-freq.h>
33 u32 mask = 0xffffffff >> (32 - nr_bits); in bit_mask()
41 unsigned long rate = clk_get_rate(clk->parent); in s3c_getrate_clksrc()
42 u32 clkdiv = __raw_readl(sclk->reg_div.reg); in s3c_getrate_clksrc()
43 u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size); in s3c_getrate_clksrc()
46 clkdiv >>= sclk->reg_div.shift; in s3c_getrate_clksrc()
56 void __iomem *reg = sclk->reg_div.reg; in s3c_setrate_clksrc()
[all …]
|
| /linux-3.3/arch/arm/mach-imx/ |
| D | clock-mx51-mx53.c | 2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
9 * http://www.opensource.org/licenses/gpl-license.html
24 #include <mach/clock.h>
26 #include "crm-regs-imx5.h"
28 /* External clock values passed-in by the board code */
53 static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post, in __calc_pre_post_dividers() argument
56 if (div >= max_pre * max_post) { in __calc_pre_post_dividers()
59 } else if (div >= max_pre) { in __calc_pre_post_dividers()
61 min_pre = DIV_ROUND_UP(div, max_post); in __calc_pre_post_dividers()
[all …]
|
| D | clock-imx1.c | 15 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
27 #include <mach/clock.h>
70 reg = __raw_readl(clk->enable_reg); in _clk_enable()
71 reg |= 1 << clk->enable_shift; in _clk_enable()
72 __raw_writel(reg, clk->enable_reg); in _clk_enable()
81 reg = __raw_readl(clk->enable_reg); in _clk_disable()
82 reg &= ~(1 << clk->enable_shift); in _clk_disable()
83 __raw_writel(reg, clk->enable_reg); in _clk_disable()
95 return -EINVAL; in _clk_can_use_parent()
101 int div; in _clk_simple_round_rate() local
[all …]
|
| D | clock-imx27.c | 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
18 * MA 02110-1301, USA.
28 #include <mach/clock.h>
77 if (!clk->enable_reg) in clk_pccr_enable()
80 reg = __raw_readl(clk->enable_reg); in clk_pccr_enable()
81 reg |= 1 << clk->enable_shift; in clk_pccr_enable()
82 __raw_writel(reg, clk->enable_reg); in clk_pccr_enable()
91 if (!clk->enable_reg) in clk_pccr_disable()
94 reg = __raw_readl(clk->enable_reg); in clk_pccr_disable()
95 reg &= ~(1 << clk->enable_shift); in clk_pccr_disable()
[all …]
|
| /linux-3.3/drivers/usb/host/ |
| D | octeon2-common.c | 14 #include <asm/octeon/cvmx-uctlx-defs.h>
22 u64 div; in octeon2_usb_clocks_start() local
49 /* Step 3: Configure the reference clock, PHY, and HCLK */ in octeon2_usb_clocks_start()
75 div = octeon_get_io_clock_rate() / 130000000ull; in octeon2_usb_clocks_start()
77 switch (div) { in octeon2_usb_clocks_start()
79 div = 1; in octeon2_usb_clocks_start()
87 div = 4; in octeon2_usb_clocks_start()
91 div = 6; in octeon2_usb_clocks_start()
97 div = 8; in octeon2_usb_clocks_start()
100 div = 12; in octeon2_usb_clocks_start()
[all …]
|
| /linux-3.3/arch/arm/mach-s3c2440/ |
| D | clock.c | 1 /* linux/arch/arm/mach-s3c2440/clock.c
3 * Copyright (c) 2004-2005 Simtec Electronics
7 * S3C2440 Clock support
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
42 #include <mach/regs-clock.h>
44 #include <plat/clock.h>
46 #include <plat/regs-serial.h>
48 /* S3C2440 extended clock support */
53 unsigned long parent_rate = clk_get_rate(clk->parent); in s3c2440_camif_upll_round()
54 int div; in s3c2440_camif_upll_round() local
[all …]
|
| /linux-3.3/arch/arm/mach-omap1/ |
| D | clock.c | 2 * linux/arch/arm/mach-omap1/clock.c
4 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
7 * Modified to use omap shared clock framework by
22 #include <asm/mach-types.h>
26 #include <plat/clock.h>
30 #include "clock.h"
37 * Omap1 specific clock functions
42 unsigned int val = __raw_readl(clk->enable_reg); in omap1_uart_recalc()
43 return val & clk->enable_bit ? 48000000 : 12000000; in omap1_uart_recalc()
48 u32 div = omap_readl(MOD_CONF_CTRL_1); in omap1_sossi_recalc() local
[all …]
|
| /linux-3.3/arch/powerpc/boot/ |
| D | cuboot-acadia.c | 2 * Old U-boot compatibility for Acadia
26 #define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
34 #define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */
35 #define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */
36 #define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */
37 #define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */
49 unsigned long div; /* total divisor udiv * bdiv */ in get_clocks() local
113 /* There is a bug in U-Boot that prevents us from using in get_clocks()
114 * bd.bi_opbfreq because U-Boot doesn't populate it for in get_clocks()
126 if (getprop(np, "current-speed", &baud, sizeof(baud)) != sizeof(baud)) in get_clocks()
[all …]
|