1 /* linux/arch/arm/plat-s3c24xx/clock-dclk.c
3  * Copyright (c) 2004-2008 Simtec Electronics
11  * S3C24XX - definitions for DCLK and CLKOUT registers
19 #include <mach/regs-clock.h>
20 #include <mach/regs-gpio.h>
22 #include <plat/clock.h>
32 		dclkcon |= clk->ctrlbit;  in s3c24xx_dclk_enable()
34 		dclkcon &= ~clk->ctrlbit;  in s3c24xx_dclk_enable()
51 		return -EINVAL;  in s3c24xx_dclk_setparent()
53 	clk->parent = parent;  in s3c24xx_dclk_setparent()
57 	if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {  in s3c24xx_dclk_setparent()
75 	unsigned long div;  in s3c24xx_calc_div()  local
77 	if ((rate == 0) || !clk->parent)  in s3c24xx_calc_div()
80 	div = clk_get_rate(clk->parent) / rate;  in s3c24xx_calc_div()
81 	if (div < 2)  in s3c24xx_calc_div()
82 		div = 2;  in s3c24xx_calc_div()
83 	else if (div > 16)  in s3c24xx_calc_div()
84 		div = 16;  in s3c24xx_calc_div()
86 	return div;  in s3c24xx_calc_div()
92 	unsigned long div = s3c24xx_calc_div(clk, rate);  in s3c24xx_round_dclk_rate()  local
94 	if (div == 0)  in s3c24xx_round_dclk_rate()
97 	return clk_get_rate(clk->parent) / div;  in s3c24xx_round_dclk_rate()
102 	unsigned long mask, data, div = s3c24xx_calc_div(clk, rate);  in s3c24xx_set_dclk_rate()  local
104 	if (div == 0)  in s3c24xx_set_dclk_rate()
105 		return -EINVAL;  in s3c24xx_set_dclk_rate()
110 		data = S3C2410_DCLKCON_DCLK0_DIV(div) |  in s3c24xx_set_dclk_rate()
111 			S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2);  in s3c24xx_set_dclk_rate()
115 		data = S3C2410_DCLKCON_DCLK1_DIV(div) |  in s3c24xx_set_dclk_rate()
116 			S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2);  in s3c24xx_set_dclk_rate()
118 		return -EINVAL;  in s3c24xx_set_dclk_rate()
120 	clk->rate = clk_get_rate(clk->parent) / div;  in s3c24xx_set_dclk_rate()
123 	return clk->rate;  in s3c24xx_set_dclk_rate()
130 	/* calculate the MISCCR setting for the clock */  in s3c24xx_clkout_setparent()
147 		return -EINVAL;  in s3c24xx_clkout_setparent()
149 	clk->parent = parent;  in s3c24xx_clkout_setparent()
162 /* external clock definitions */