Lines Matching +full:clock +full:- +full:div
15 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
27 #include <mach/clock.h>
70 reg = __raw_readl(clk->enable_reg); in _clk_enable()
71 reg |= 1 << clk->enable_shift; in _clk_enable()
72 __raw_writel(reg, clk->enable_reg); in _clk_enable()
81 reg = __raw_readl(clk->enable_reg); in _clk_disable()
82 reg &= ~(1 << clk->enable_shift); in _clk_disable()
83 __raw_writel(reg, clk->enable_reg); in _clk_disable()
95 return -EINVAL; in _clk_can_use_parent()
101 int div; in _clk_simple_round_rate() local
104 parent_rate = clk_get_rate(clk->parent); in _clk_simple_round_rate()
106 div = parent_rate / rate; in _clk_simple_round_rate()
108 div++; in _clk_simple_round_rate()
110 if (div > limit) in _clk_simple_round_rate()
111 div = limit; in _clk_simple_round_rate()
113 return parent_rate / div; in _clk_simple_round_rate()
118 return clk->parent->round_rate(clk->parent, rate); in _clk_parent_round_rate()
123 return clk->parent->set_rate(clk->parent, rate); in _clk_parent_set_rate()
153 return clk_get_rate(clk->parent) * 512; in clk32_premult_get_rate()
197 clk_get_rate(clk->parent)); in system_clk_get_rate()
208 clk_get_rate(clk->parent)); in mcu_clk_get_rate()
218 unsigned long fclk = clk_get_rate(clk->parent); in fclk_get_rate()
236 return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) & in hclk_get_rate()
247 unsigned int div; in hclk_set_rate() local
251 parent_rate = clk_get_rate(clk->parent); in hclk_set_rate()
253 div = parent_rate / rate; in hclk_set_rate()
255 if (div > 16 || div < 1 || ((parent_rate / div) != rate)) in hclk_set_rate()
256 return -EINVAL; in hclk_set_rate()
258 div--; in hclk_set_rate()
262 reg |= div << CCM_CSCR_BCLK_OFFSET; in hclk_set_rate()
277 return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) & in clk48m_get_rate()
288 unsigned int div; in clk48m_set_rate() local
292 parent_rate = clk_get_rate(clk->parent); in clk48m_set_rate()
294 div = parent_rate / rate; in clk48m_set_rate()
296 if (div > 8 || div < 1 || ((parent_rate / div) != rate)) in clk48m_set_rate()
297 return -EINVAL; in clk48m_set_rate()
299 div--; in clk48m_set_rate()
303 reg |= div << CCM_CSCR_USB_OFFSET; in clk48m_set_rate()
317 * get peripheral clock 1 ( UART[12], Timer[12], PWM )
321 return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) & in perclk1_get_rate()
332 unsigned int div; in perclk1_set_rate() local
336 parent_rate = clk_get_rate(clk->parent); in perclk1_set_rate()
338 div = parent_rate / rate; in perclk1_set_rate()
340 if (div > 16 || div < 1 || ((parent_rate / div) != rate)) in perclk1_set_rate()
341 return -EINVAL; in perclk1_set_rate()
343 div--; in perclk1_set_rate()
347 reg |= div << CCM_PCDR_PCLK1_OFFSET; in perclk1_set_rate()
354 * get peripheral clock 2 ( LCD, SD, SPI[12] )
358 return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) & in perclk2_get_rate()
369 unsigned int div; in perclk2_set_rate() local
373 parent_rate = clk_get_rate(clk->parent); in perclk2_set_rate()
375 div = parent_rate / rate; in perclk2_set_rate()
377 if (div > 16 || div < 1 || ((parent_rate / div) != rate)) in perclk2_set_rate()
378 return -EINVAL; in perclk2_set_rate()
380 div--; in perclk2_set_rate()
384 reg |= div << CCM_PCDR_PCLK2_OFFSET; in perclk2_set_rate()
391 * get peripheral clock 3 ( SSI )
395 return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) & in perclk3_get_rate()
406 unsigned int div; in perclk3_set_rate() local
410 parent_rate = clk_get_rate(clk->parent); in perclk3_set_rate()
412 div = parent_rate / rate; in perclk3_set_rate()
414 if (div > 128 || div < 1 || ((parent_rate / div) != rate)) in perclk3_set_rate()
415 return -EINVAL; in perclk3_set_rate()
417 div--; in perclk3_set_rate()
421 reg |= div << CCM_PCDR_PCLK3_OFFSET; in perclk3_set_rate()
471 if (clko_clocks[i]->set_rate && clko_clocks[i]->round_rate) { in clko_set_parent()
472 clk->set_rate = _clk_parent_set_rate; in clko_set_parent()
473 clk->round_rate = _clk_parent_round_rate; in clko_set_parent()
475 clk->set_rate = NULL; in clko_set_parent()
476 clk->round_rate = NULL; in clko_set_parent()
586 _REGISTER_CLOCK("mx1-camera.0", NULL, csi_clk)
590 _REGISTER_CLOCK("imx1-uart.0", NULL, uart_clk)
591 _REGISTER_CLOCK("imx1-uart.1", NULL, uart_clk)
592 _REGISTER_CLOCK("imx1-uart.2", NULL, uart_clk)
593 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
594 _REGISTER_CLOCK("imx1-cspi.0", NULL, spi_clk)
595 _REGISTER_CLOCK("imx1-cspi.1", NULL, spi_clk)
596 _REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk)
597 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
613 /* detect clock reference for system PLL */ in mx1_clocks_init()