Lines Matching +full:clock +full:- +full:div

14 #include <asm/octeon/cvmx-uctlx-defs.h>
22 	u64 div;  in octeon2_usb_clocks_start()  local
49 	/* Step 3: Configure the reference clock, PHY, and HCLK */  in octeon2_usb_clocks_start()
75 	div = octeon_get_io_clock_rate() / 130000000ull;  in octeon2_usb_clocks_start()
77 	switch (div) {  in octeon2_usb_clocks_start()
79 		div = 1;  in octeon2_usb_clocks_start()
87 		div = 4;  in octeon2_usb_clocks_start()
91 		div = 6;  in octeon2_usb_clocks_start()
97 		div = 8;  in octeon2_usb_clocks_start()
100 		div = 12;  in octeon2_usb_clocks_start()
103 	clk_rst_ctl.s.h_div = div;  in octeon2_usb_clocks_start()
117 	 * Step 4: Program the power-on reset field in the UCTL  in octeon2_usb_clocks_start()
118 	 * clock-reset-control register.  in octeon2_usb_clocks_start()
123 	/* Step 5:    Wait 1 ms for the PHY clock to start. */  in octeon2_usb_clocks_start()
142 	 * Step 9: Wait for at least 20ns for UPHY to output PHY clock  in octeon2_usb_clocks_start()
197 	octeon2_usb_clock_start_cnt--;  in octeon2_usb_clocks_stop()