2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
18  * MA 02110-1301, USA.
28 #include <mach/clock.h>
77 	if (!clk->enable_reg)  in clk_pccr_enable()
80 	reg = __raw_readl(clk->enable_reg);  in clk_pccr_enable()
81 	reg |= 1 << clk->enable_shift;  in clk_pccr_enable()
82 	__raw_writel(reg, clk->enable_reg);  in clk_pccr_enable()
91 	if (!clk->enable_reg)  in clk_pccr_disable()
94 	reg = __raw_readl(clk->enable_reg);  in clk_pccr_disable()
95 	reg &= ~(1 << clk->enable_shift);  in clk_pccr_disable()
96 	__raw_writel(reg, clk->enable_reg);  in clk_pccr_disable()
125 	if (clk->parent == parent)  in clk_cpu_set_parent()
135 				return -EINVAL;  in clk_cpu_set_parent()
138 		clk->parent = parent;  in clk_cpu_set_parent()
141 	return -ENODEV;  in clk_cpu_set_parent()
146 	int div;  in round_rate_cpu()  local
149 	parent_rate = clk_get_rate(clk->parent);  in round_rate_cpu()
151 	div = parent_rate / rate;  in round_rate_cpu()
153 		div++;  in round_rate_cpu()
155 	if (div > 4)  in round_rate_cpu()
156 		div = 4;  in round_rate_cpu()
158 	return parent_rate / div;  in round_rate_cpu()
163 	unsigned int div;  in set_rate_cpu()  local
167 	parent_rate = clk_get_rate(clk->parent);  in set_rate_cpu()
169 	div = parent_rate / rate;  in set_rate_cpu()
171 	if (div > 4 || div < 1 || ((parent_rate / div) != rate))  in set_rate_cpu()
172 		return -EINVAL;  in set_rate_cpu()
174 	div--;  in set_rate_cpu()
179 		reg |= div << 12;  in set_rate_cpu()
191 	u32 div;  in round_rate_per()  local
194 	parent_rate = clk_get_rate(clk->parent);  in round_rate_per()
196 	div = parent_rate / rate;  in round_rate_per()
198 		div++;  in round_rate_per()
200 	if (div > 64)  in round_rate_per()
201 		div = 64;  in round_rate_per()
203 	return parent_rate / div;  in round_rate_per()
209 	u32 div;  in set_rate_per()  local
212 	parent_rate = clk_get_rate(clk->parent);  in set_rate_per()
214 	if (clk->id < 0 || clk->id > 3)  in set_rate_per()
215 		return -EINVAL;  in set_rate_per()
217 	div = parent_rate / rate;  in set_rate_per()
218 	if (div > 64 || div < 1 || ((parent_rate / div) != rate))  in set_rate_per()
219 		return -EINVAL;  in set_rate_per()
220 	div--;  in set_rate_per()
222 	reg = __raw_readl(CCM_PCDR1) & ~(0x3f << (clk->id << 3));  in set_rate_per()
223 	reg |= div << (clk->id << 3);  in set_rate_per()
234 	parent_rate = clk_get_rate(clk->parent);  in get_rate_usb()
245 	parent_rate = clk_get_rate(clk->parent);  in get_rate_ssix()
270 	parent_rate = clk_get_rate(clk->parent);  in get_rate_nfc()
285 	parent_rate = clk_get_rate(clk->parent);  in get_rate_vpu()
300 	return clk->parent->round_rate(clk->parent, rate);  in round_rate_parent()
305 	return clk_get_rate(clk->parent);  in get_rate_parent()
310 	return clk->parent->set_rate(clk->parent, rate);  in set_rate_parent()
331 	return clk_get_rate(clk->parent) * 1024;  in get_rate_fpm()
337 			clk_get_rate(clk->parent));  in get_rate_mpll()
344 	parent_rate = clk_get_rate(clk->parent);  in get_rate_mpll_main()
347 	 * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2  in get_rate_mpll_main()
348 	 * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3  in get_rate_mpll_main()
350 	if (mx27_revision() >= IMX_CHIP_REVISION_2_0 && clk->id == 1)  in get_rate_mpll_main()
361 	rate = clk_get_rate(clk->parent);  in get_rate_spll()
376 	u32 div;  in get_rate_cpu()  local
380 		div = (__raw_readl(CCM_CSCR) >> 12) & 0x3;  in get_rate_cpu()
382 		div = (__raw_readl(CCM_CSCR) >> 13) & 0x7;  in get_rate_cpu()
384 	rate = clk_get_rate(clk->parent);  in get_rate_cpu()
385 	return rate / (div + 1);  in get_rate_cpu()
397 	rate = clk_get_rate(clk->parent);  in get_rate_ahb()
406 		return clk_get_rate(clk->parent);  in get_rate_ipg()
410 	rate = clk_get_rate(clk->parent);  in get_rate_ipg()
418 	parent_rate = clk_get_rate(clk->parent);  in get_rate_per()
420 	if (clk->id < 0 || clk->id > 3)  in get_rate_per()
423 	perclk_pdf = (__raw_readl(CCM_PCDR1) >> (clk->id << 3)) & 0x3f;  in get_rate_per()
429  * the high frequency external clock reference
443  * It provides the clock source whose rate is same as MPLL
452  * It provides the clock source whose rate is same MPLL * 2 / 3
486  * the low frequency external clock reference
628 	_REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
629 	_REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
630 	_REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
631 	_REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
632 	_REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
633 	_REGISTER_CLOCK("imx21-uart.5", NULL, uart6_clk)
641 	_REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
642 	_REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
643 	_REGISTER_CLOCK("mxc-mmc.2", NULL, sdhc3_clk)
644 	_REGISTER_CLOCK("imx27-cspi.0", NULL, cspi1_clk)
645 	_REGISTER_CLOCK("imx27-cspi.1", NULL, cspi2_clk)
646 	_REGISTER_CLOCK("imx27-cspi.2", NULL, cspi3_clk)
647 	_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
648 	_REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
649 	_REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)
650 	_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1)
651 	_REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk)
652 	_REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk1)
653 	_REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk)
654 	_REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk1)
655 	_REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk)
656 	_REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk1)
657 	_REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
658 	_REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
666 	_REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk)
671 	_REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
673 	_REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
674 	_REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
682 /* Adjust the clock path for TO2 and later */
720  * available clock rate when the timer framework starts
728 	/* detect clock reference for both system PLLs */  in mx27_clocks_init()