1 /* linux/arch/arm/plat-samsung/clock-clksrc.c
22 #include <plat/clock.h>
23 #include <plat/clock-clksrc.h>
24 #include <plat/cpu-freq.h>
33 	u32 mask = 0xffffffff >> (32 - nr_bits);  in bit_mask()
41 	unsigned long rate = clk_get_rate(clk->parent);  in s3c_getrate_clksrc()
42 	u32 clkdiv = __raw_readl(sclk->reg_div.reg);  in s3c_getrate_clksrc()
43 	u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size);  in s3c_getrate_clksrc()
46 	clkdiv >>= sclk->reg_div.shift;  in s3c_getrate_clksrc()
56 	void __iomem *reg = sclk->reg_div.reg;  in s3c_setrate_clksrc()
57 	unsigned int div;  in s3c_setrate_clksrc()  local
58 	u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size);  in s3c_setrate_clksrc()
62 	div = clk_get_rate(clk->parent) / rate;  in s3c_setrate_clksrc()
63 	if (div > (1 << sclk->reg_div.size))  in s3c_setrate_clksrc()
64 		return -EINVAL;  in s3c_setrate_clksrc()
68 	val |= (div - 1) << sclk->reg_div.shift;  in s3c_setrate_clksrc()
77 	struct clksrc_sources *srcs = sclk->sources;  in s3c_setparent_clksrc()
78 	u32 clksrc = __raw_readl(sclk->reg_src.reg);  in s3c_setparent_clksrc()
79 	u32 mask = bit_mask(sclk->reg_src.shift, sclk->reg_src.size);  in s3c_setparent_clksrc()
80 	int src_nr = -1;  in s3c_setparent_clksrc()
83 	for (ptr = 0; ptr < srcs->nr_sources; ptr++)  in s3c_setparent_clksrc()
84 		if (srcs->sources[ptr] == parent) {  in s3c_setparent_clksrc()
90 		clk->parent = parent;  in s3c_setparent_clksrc()
93 		clksrc |= src_nr << sclk->reg_src.shift;  in s3c_setparent_clksrc()
95 		__raw_writel(clksrc, sclk->reg_src.reg);  in s3c_setparent_clksrc()
99 	return -EINVAL;  in s3c_setparent_clksrc()
106 	unsigned long parent_rate = clk_get_rate(clk->parent);  in s3c_roundrate_clksrc()
107 	int max_div = 1 << sclk->reg_div.size;  in s3c_roundrate_clksrc()
108 	int div;  in s3c_roundrate_clksrc()  local
113 		div = parent_rate / rate;  in s3c_roundrate_clksrc()
115 			div++;  in s3c_roundrate_clksrc()
117 		if (div == 0)  in s3c_roundrate_clksrc()
118 			div = 1;  in s3c_roundrate_clksrc()
119 		if (div > max_div)  in s3c_roundrate_clksrc()
120 			div = max_div;  in s3c_roundrate_clksrc()
122 		rate = parent_rate / div;  in s3c_roundrate_clksrc()
128 /* Clock initialisation code */
132 	struct clksrc_sources *srcs = clk->sources;  in s3c_set_clksrc()
133 	u32 mask = bit_mask(clk->reg_src.shift, clk->reg_src.size);  in s3c_set_clksrc()
136 	if (!clk->reg_src.reg) {  in s3c_set_clksrc()
137 		if (!clk->clk.parent)  in s3c_set_clksrc()
138 			printk(KERN_ERR "%s: no parent clock specified\n",  in s3c_set_clksrc()
139 				clk->clk.name);  in s3c_set_clksrc()
143 	clksrc = __raw_readl(clk->reg_src.reg);  in s3c_set_clksrc()
145 	clksrc >>= clk->reg_src.shift;  in s3c_set_clksrc()
147 	if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {  in s3c_set_clksrc()
149 		       clk->clk.name, clksrc);  in s3c_set_clksrc()
153 	clk->clk.parent = srcs->sources[clksrc];  in s3c_set_clksrc()
157 		       clk->clk.name, clk->clk.parent->name, clksrc,  in s3c_set_clksrc()
158 		       clk_get_rate(&clk->clk));  in s3c_set_clksrc()
182 	for (; size > 0; size--, clksrc++) {  in s3c_register_clksrc()
183 		if (!clksrc->reg_div.reg && !clksrc->reg_src.reg)  in s3c_register_clksrc()
184 			printk(KERN_ERR "%s: clock %s has no registers set\n",  in s3c_register_clksrc()
185 			       __func__, clksrc->clk.name);  in s3c_register_clksrc()
189 		if (!clksrc->clk.ops) {  in s3c_register_clksrc()
190 			if (!clksrc->reg_div.reg)  in s3c_register_clksrc()
191 				clksrc->clk.ops = &clksrc_ops_nodiv;  in s3c_register_clksrc()
192 			else if (!clksrc->reg_src.reg)  in s3c_register_clksrc()
193 				clksrc->clk.ops = &clksrc_ops_nosrc;  in s3c_register_clksrc()
195 				clksrc->clk.ops = &clksrc_ops;  in s3c_register_clksrc()
199 		 * as it may be re-set by the setup routines  in s3c_register_clksrc()
205 		ret = s3c24xx_register_clock(&clksrc->clk);  in s3c_register_clksrc()
209 			       __func__, clksrc->clk.name, ret);  in s3c_register_clksrc()