1 /* linux/arch/arm/plat-s3c24xx/s3c2443-clock.c
6  * S3C2443 Clock control suport - common code
13 #include <mach/regs-s3c2443-clock.h>
16 #include <plat/clock.h>
17 #include <plat/clock-clksrc.h>
20 #include <plat/cpu-freq.h>
25 	u32 ctrlbit = clk->ctrlbit;  in s3c2443_gate()
81  * this is sourced from either the EPLL or the EPLLref clock
103 	unsigned long parent_rate = clk_get_rate(clk->parent);  in s3c2443_getrate_mdivclk()
104 	unsigned long div = __raw_readl(S3C2443_CLKDIV0);  in s3c2443_getrate_mdivclk()  local
106 	div  &= S3C2443_CLKDIV0_EXTDIV_MASK;  in s3c2443_getrate_mdivclk()
107 	div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1);	/* x2 */  in s3c2443_getrate_mdivclk()
109 	return parent_rate / (div + 1);  in s3c2443_getrate_mdivclk()
146 	unsigned long rate = clk_get_rate(clk->parent);  in s3c2443_prediv_getrate()
165  * this clock is sourced from msysclk and can have a number of
176 	unsigned long parent = clk_get_rate(clk->parent);  in s3c2443_armclk_roundrate()
179 	unsigned div;  in s3c2443_armclk_roundrate()  local
183 		return -EINVAL;  in s3c2443_armclk_roundrate()
186 		div = armdiv[ptr];  in s3c2443_armclk_roundrate()
187 		if (div) {  in s3c2443_armclk_roundrate()
189 			calc = (parent / div / 1000) * 1000;  in s3c2443_armclk_roundrate()
190 			if (calc <= rate && div < best)  in s3c2443_armclk_roundrate()
191 				best = div;  in s3c2443_armclk_roundrate()
200 	unsigned long rate = clk_get_rate(clk->parent);  in s3c2443_armclk_getrate()
205 		return -EINVAL;  in s3c2443_armclk_getrate()
216 	unsigned long parent = clk_get_rate(clk->parent);  in s3c2443_armclk_setrate()
218 	unsigned div;  in s3c2443_armclk_setrate()  local
221 	int val = -1;  in s3c2443_armclk_setrate()
224 		return -EINVAL;  in s3c2443_armclk_setrate()
227 		div = armdiv[ptr];  in s3c2443_armclk_setrate()
228 		if (div) {  in s3c2443_armclk_setrate()
230 			calc = (parent / div / 1000) * 1000;  in s3c2443_armclk_setrate()
231 			if (calc <= rate && div < best) {  in s3c2443_armclk_setrate()
232 				best = div;  in s3c2443_armclk_setrate()
247 	return (val == -1) ? -EINVAL : 0;  in s3c2443_armclk_setrate()
262  * this is the clock fed into the ARM core itself, from armdiv or from hclk.
283  * usb host bus-clock, usually 48MHz to provide USB bus clock timing
288 		.name		= "usb-bus-host-parent",
300 		/* camera interface bus-clock, divided down from esysclk */
302 			.name		= "camif-upll",	/* same as 2440 name */
310 			.name		= "display-if",
320 	/* ART baud-rate clock sourced from esysclk via a divisor */
329 	.name		= "i2s-ext",
334  * This clock is the output from the I2S divisor of ESYSCLK, and is separate
335  * from the mux that comes after it (cannot merge into one single clock)
340 		.name		= "i2s-eplldiv",
346 /* i2s-ref
348  * i2s bus reference clock, selectable from external, esysclk or epllref
362 		.name		= "i2s-if",
435 		.name		= "usb-host",
440 		.name		= "usb-device",
467 		.devname	= "s3c2440-uart.0",
473 		.devname	= "s3c2440-uart.1",
479 		.devname	= "s3c2440-uart.2",
485 		.devname	= "s3c2440-uart.3",
506 		.name		= "usb-bus-host",
513 	.devname	= "s3c-sdhci.1",
563 	/* ensure usb bus clock is within correct rate of 48MHz */  in s3c2443_common_setup_clocks()
570 	printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",  in s3c2443_common_setup_clocks()
601 	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),