1 /* linux/arch/arm/plat-s3c24xx/s3c2443-clock.c
2 *
3 * Copyright (c) 2007, 2010 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2443 Clock control suport - common code
7 */
8
9 #include <linux/init.h>
10 #include <linux/clk.h>
11 #include <linux/io.h>
12
13 #include <mach/regs-s3c2443-clock.h>
14
15 #include <plat/s3c2443.h>
16 #include <plat/clock.h>
17 #include <plat/clock-clksrc.h>
18 #include <plat/cpu.h>
19
20 #include <plat/cpu-freq.h>
21
22
s3c2443_gate(void __iomem * reg,struct clk * clk,int enable)23 static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable)
24 {
25 u32 ctrlbit = clk->ctrlbit;
26 u32 con = __raw_readl(reg);
27
28 if (enable)
29 con |= ctrlbit;
30 else
31 con &= ~ctrlbit;
32
33 __raw_writel(con, reg);
34 return 0;
35 }
36
s3c2443_clkcon_enable_h(struct clk * clk,int enable)37 int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
38 {
39 return s3c2443_gate(S3C2443_HCLKCON, clk, enable);
40 }
41
s3c2443_clkcon_enable_p(struct clk * clk,int enable)42 int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
43 {
44 return s3c2443_gate(S3C2443_PCLKCON, clk, enable);
45 }
46
s3c2443_clkcon_enable_s(struct clk * clk,int enable)47 int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
48 {
49 return s3c2443_gate(S3C2443_SCLKCON, clk, enable);
50 }
51
52 /* mpllref is a direct descendant of clk_xtal by default, but it is not
53 * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
54 * such directly equating the two source clocks is impossible.
55 */
56 struct clk clk_mpllref = {
57 .name = "mpllref",
58 .parent = &clk_xtal,
59 };
60
61 static struct clk *clk_epllref_sources[] = {
62 [0] = &clk_mpllref,
63 [1] = &clk_mpllref,
64 [2] = &clk_xtal,
65 [3] = &clk_ext,
66 };
67
68 struct clksrc_clk clk_epllref = {
69 .clk = {
70 .name = "epllref",
71 },
72 .sources = &(struct clksrc_sources) {
73 .sources = clk_epllref_sources,
74 .nr_sources = ARRAY_SIZE(clk_epllref_sources),
75 },
76 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 },
77 };
78
79 /* esysclk
80 *
81 * this is sourced from either the EPLL or the EPLLref clock
82 */
83
84 static struct clk *clk_sysclk_sources[] = {
85 [0] = &clk_epllref.clk,
86 [1] = &clk_epll,
87 };
88
89 struct clksrc_clk clk_esysclk = {
90 .clk = {
91 .name = "esysclk",
92 .parent = &clk_epll,
93 },
94 .sources = &(struct clksrc_sources) {
95 .sources = clk_sysclk_sources,
96 .nr_sources = ARRAY_SIZE(clk_sysclk_sources),
97 },
98 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 },
99 };
100
s3c2443_getrate_mdivclk(struct clk * clk)101 static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
102 {
103 unsigned long parent_rate = clk_get_rate(clk->parent);
104 unsigned long div = __raw_readl(S3C2443_CLKDIV0);
105
106 div &= S3C2443_CLKDIV0_EXTDIV_MASK;
107 div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */
108
109 return parent_rate / (div + 1);
110 }
111
112 static struct clk clk_mdivclk = {
113 .name = "mdivclk",
114 .parent = &clk_mpllref,
115 .ops = &(struct clk_ops) {
116 .get_rate = s3c2443_getrate_mdivclk,
117 },
118 };
119
120 static struct clk *clk_msysclk_sources[] = {
121 [0] = &clk_mpllref,
122 [1] = &clk_mpll,
123 [2] = &clk_mdivclk,
124 [3] = &clk_mpllref,
125 };
126
127 struct clksrc_clk clk_msysclk = {
128 .clk = {
129 .name = "msysclk",
130 .parent = &clk_xtal,
131 },
132 .sources = &(struct clksrc_sources) {
133 .sources = clk_msysclk_sources,
134 .nr_sources = ARRAY_SIZE(clk_msysclk_sources),
135 },
136 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 },
137 };
138
139 /* prediv
140 *
141 * this divides the msysclk down to pass to h/p/etc.
142 */
143
s3c2443_prediv_getrate(struct clk * clk)144 static unsigned long s3c2443_prediv_getrate(struct clk *clk)
145 {
146 unsigned long rate = clk_get_rate(clk->parent);
147 unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
148
149 clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
150 clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
151
152 return rate / (clkdiv0 + 1);
153 }
154
155 static struct clk clk_prediv = {
156 .name = "prediv",
157 .parent = &clk_msysclk.clk,
158 .ops = &(struct clk_ops) {
159 .get_rate = s3c2443_prediv_getrate,
160 },
161 };
162
163 /* armdiv
164 *
165 * this clock is sourced from msysclk and can have a number of
166 * divider values applied to it to then be fed into armclk.
167 */
168
169 static unsigned int *armdiv;
170 static int nr_armdiv;
171 static int armdivmask;
172
s3c2443_armclk_roundrate(struct clk * clk,unsigned long rate)173 static unsigned long s3c2443_armclk_roundrate(struct clk *clk,
174 unsigned long rate)
175 {
176 unsigned long parent = clk_get_rate(clk->parent);
177 unsigned long calc;
178 unsigned best = 256; /* bigger than any value */
179 unsigned div;
180 int ptr;
181
182 if (!nr_armdiv)
183 return -EINVAL;
184
185 for (ptr = 0; ptr < nr_armdiv; ptr++) {
186 div = armdiv[ptr];
187 if (div) {
188 /* cpufreq provides 266mhz as 266666000 not 266666666 */
189 calc = (parent / div / 1000) * 1000;
190 if (calc <= rate && div < best)
191 best = div;
192 }
193 }
194
195 return parent / best;
196 }
197
s3c2443_armclk_getrate(struct clk * clk)198 static unsigned long s3c2443_armclk_getrate(struct clk *clk)
199 {
200 unsigned long rate = clk_get_rate(clk->parent);
201 unsigned long clkcon0;
202 int val;
203
204 if (!nr_armdiv || !armdivmask)
205 return -EINVAL;
206
207 clkcon0 = __raw_readl(S3C2443_CLKDIV0);
208 clkcon0 &= armdivmask;
209 val = clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT;
210
211 return rate / armdiv[val];
212 }
213
s3c2443_armclk_setrate(struct clk * clk,unsigned long rate)214 static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
215 {
216 unsigned long parent = clk_get_rate(clk->parent);
217 unsigned long calc;
218 unsigned div;
219 unsigned best = 256; /* bigger than any value */
220 int ptr;
221 int val = -1;
222
223 if (!nr_armdiv || !armdivmask)
224 return -EINVAL;
225
226 for (ptr = 0; ptr < nr_armdiv; ptr++) {
227 div = armdiv[ptr];
228 if (div) {
229 /* cpufreq provides 266mhz as 266666000 not 266666666 */
230 calc = (parent / div / 1000) * 1000;
231 if (calc <= rate && div < best) {
232 best = div;
233 val = ptr;
234 }
235 }
236 }
237
238 if (val >= 0) {
239 unsigned long clkcon0;
240
241 clkcon0 = __raw_readl(S3C2443_CLKDIV0);
242 clkcon0 &= ~armdivmask;
243 clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
244 __raw_writel(clkcon0, S3C2443_CLKDIV0);
245 }
246
247 return (val == -1) ? -EINVAL : 0;
248 }
249
250 static struct clk clk_armdiv = {
251 .name = "armdiv",
252 .parent = &clk_msysclk.clk,
253 .ops = &(struct clk_ops) {
254 .round_rate = s3c2443_armclk_roundrate,
255 .get_rate = s3c2443_armclk_getrate,
256 .set_rate = s3c2443_armclk_setrate,
257 },
258 };
259
260 /* armclk
261 *
262 * this is the clock fed into the ARM core itself, from armdiv or from hclk.
263 */
264
265 static struct clk *clk_arm_sources[] = {
266 [0] = &clk_armdiv,
267 [1] = &clk_h,
268 };
269
270 static struct clksrc_clk clk_arm = {
271 .clk = {
272 .name = "armclk",
273 },
274 .sources = &(struct clksrc_sources) {
275 .sources = clk_arm_sources,
276 .nr_sources = ARRAY_SIZE(clk_arm_sources),
277 },
278 .reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 },
279 };
280
281 /* usbhost
282 *
283 * usb host bus-clock, usually 48MHz to provide USB bus clock timing
284 */
285
286 static struct clksrc_clk clk_usb_bus_host = {
287 .clk = {
288 .name = "usb-bus-host-parent",
289 .parent = &clk_esysclk.clk,
290 .ctrlbit = S3C2443_SCLKCON_USBHOST,
291 .enable = s3c2443_clkcon_enable_s,
292 },
293 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
294 };
295
296 /* common clksrc clocks */
297
298 static struct clksrc_clk clksrc_clks[] = {
299 {
300 /* camera interface bus-clock, divided down from esysclk */
301 .clk = {
302 .name = "camif-upll", /* same as 2440 name */
303 .parent = &clk_esysclk.clk,
304 .ctrlbit = S3C2443_SCLKCON_CAMCLK,
305 .enable = s3c2443_clkcon_enable_s,
306 },
307 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 },
308 }, {
309 .clk = {
310 .name = "display-if",
311 .parent = &clk_esysclk.clk,
312 .ctrlbit = S3C2443_SCLKCON_DISPCLK,
313 .enable = s3c2443_clkcon_enable_s,
314 },
315 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 },
316 },
317 };
318
319 static struct clksrc_clk clk_esys_uart = {
320 /* ART baud-rate clock sourced from esysclk via a divisor */
321 .clk = {
322 .name = "uartclk",
323 .parent = &clk_esysclk.clk,
324 },
325 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
326 };
327
328 static struct clk clk_i2s_ext = {
329 .name = "i2s-ext",
330 };
331
332 /* i2s_eplldiv
333 *
334 * This clock is the output from the I2S divisor of ESYSCLK, and is separate
335 * from the mux that comes after it (cannot merge into one single clock)
336 */
337
338 static struct clksrc_clk clk_i2s_eplldiv = {
339 .clk = {
340 .name = "i2s-eplldiv",
341 .parent = &clk_esysclk.clk,
342 },
343 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
344 };
345
346 /* i2s-ref
347 *
348 * i2s bus reference clock, selectable from external, esysclk or epllref
349 *
350 * Note, this used to be two clocks, but was compressed into one.
351 */
352
353 static struct clk *clk_i2s_srclist[] = {
354 [0] = &clk_i2s_eplldiv.clk,
355 [1] = &clk_i2s_ext,
356 [2] = &clk_epllref.clk,
357 [3] = &clk_epllref.clk,
358 };
359
360 static struct clksrc_clk clk_i2s = {
361 .clk = {
362 .name = "i2s-if",
363 .ctrlbit = S3C2443_SCLKCON_I2SCLK,
364 .enable = s3c2443_clkcon_enable_s,
365
366 },
367 .sources = &(struct clksrc_sources) {
368 .sources = clk_i2s_srclist,
369 .nr_sources = ARRAY_SIZE(clk_i2s_srclist),
370 },
371 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
372 };
373
374 static struct clk init_clocks_off[] = {
375 {
376 .name = "iis",
377 .parent = &clk_p,
378 .enable = s3c2443_clkcon_enable_p,
379 .ctrlbit = S3C2443_PCLKCON_IIS,
380 }, {
381 .name = "hsspi",
382 .parent = &clk_p,
383 .enable = s3c2443_clkcon_enable_p,
384 .ctrlbit = S3C2443_PCLKCON_HSSPI,
385 }, {
386 .name = "adc",
387 .parent = &clk_p,
388 .enable = s3c2443_clkcon_enable_p,
389 .ctrlbit = S3C2443_PCLKCON_ADC,
390 }, {
391 .name = "i2c",
392 .parent = &clk_p,
393 .enable = s3c2443_clkcon_enable_p,
394 .ctrlbit = S3C2443_PCLKCON_IIC,
395 }
396 };
397
398 static struct clk init_clocks[] = {
399 {
400 .name = "dma",
401 .parent = &clk_h,
402 .enable = s3c2443_clkcon_enable_h,
403 .ctrlbit = S3C2443_HCLKCON_DMA0,
404 }, {
405 .name = "dma",
406 .parent = &clk_h,
407 .enable = s3c2443_clkcon_enable_h,
408 .ctrlbit = S3C2443_HCLKCON_DMA1,
409 }, {
410 .name = "dma",
411 .parent = &clk_h,
412 .enable = s3c2443_clkcon_enable_h,
413 .ctrlbit = S3C2443_HCLKCON_DMA2,
414 }, {
415 .name = "dma",
416 .parent = &clk_h,
417 .enable = s3c2443_clkcon_enable_h,
418 .ctrlbit = S3C2443_HCLKCON_DMA3,
419 }, {
420 .name = "dma",
421 .parent = &clk_h,
422 .enable = s3c2443_clkcon_enable_h,
423 .ctrlbit = S3C2443_HCLKCON_DMA4,
424 }, {
425 .name = "dma",
426 .parent = &clk_h,
427 .enable = s3c2443_clkcon_enable_h,
428 .ctrlbit = S3C2443_HCLKCON_DMA5,
429 }, {
430 .name = "gpio",
431 .parent = &clk_p,
432 .enable = s3c2443_clkcon_enable_p,
433 .ctrlbit = S3C2443_PCLKCON_GPIO,
434 }, {
435 .name = "usb-host",
436 .parent = &clk_h,
437 .enable = s3c2443_clkcon_enable_h,
438 .ctrlbit = S3C2443_HCLKCON_USBH,
439 }, {
440 .name = "usb-device",
441 .parent = &clk_h,
442 .enable = s3c2443_clkcon_enable_h,
443 .ctrlbit = S3C2443_HCLKCON_USBD,
444 }, {
445 .name = "lcd",
446 .parent = &clk_h,
447 .enable = s3c2443_clkcon_enable_h,
448 .ctrlbit = S3C2443_HCLKCON_LCDC,
449
450 }, {
451 .name = "timers",
452 .parent = &clk_p,
453 .enable = s3c2443_clkcon_enable_p,
454 .ctrlbit = S3C2443_PCLKCON_PWMT,
455 }, {
456 .name = "cfc",
457 .parent = &clk_h,
458 .enable = s3c2443_clkcon_enable_h,
459 .ctrlbit = S3C2443_HCLKCON_CFC,
460 }, {
461 .name = "ssmc",
462 .parent = &clk_h,
463 .enable = s3c2443_clkcon_enable_h,
464 .ctrlbit = S3C2443_HCLKCON_SSMC,
465 }, {
466 .name = "uart",
467 .devname = "s3c2440-uart.0",
468 .parent = &clk_p,
469 .enable = s3c2443_clkcon_enable_p,
470 .ctrlbit = S3C2443_PCLKCON_UART0,
471 }, {
472 .name = "uart",
473 .devname = "s3c2440-uart.1",
474 .parent = &clk_p,
475 .enable = s3c2443_clkcon_enable_p,
476 .ctrlbit = S3C2443_PCLKCON_UART1,
477 }, {
478 .name = "uart",
479 .devname = "s3c2440-uart.2",
480 .parent = &clk_p,
481 .enable = s3c2443_clkcon_enable_p,
482 .ctrlbit = S3C2443_PCLKCON_UART2,
483 }, {
484 .name = "uart",
485 .devname = "s3c2440-uart.3",
486 .parent = &clk_p,
487 .enable = s3c2443_clkcon_enable_p,
488 .ctrlbit = S3C2443_PCLKCON_UART3,
489 }, {
490 .name = "rtc",
491 .parent = &clk_p,
492 .enable = s3c2443_clkcon_enable_p,
493 .ctrlbit = S3C2443_PCLKCON_RTC,
494 }, {
495 .name = "watchdog",
496 .parent = &clk_p,
497 .ctrlbit = S3C2443_PCLKCON_WDT,
498 }, {
499 .name = "ac97",
500 .parent = &clk_p,
501 .ctrlbit = S3C2443_PCLKCON_AC97,
502 }, {
503 .name = "nand",
504 .parent = &clk_h,
505 }, {
506 .name = "usb-bus-host",
507 .parent = &clk_usb_bus_host.clk,
508 }
509 };
510
511 static struct clk hsmmc1_clk = {
512 .name = "hsmmc",
513 .devname = "s3c-sdhci.1",
514 .parent = &clk_h,
515 .enable = s3c2443_clkcon_enable_h,
516 .ctrlbit = S3C2443_HCLKCON_HSMMC,
517 };
518
s3c2443_get_hdiv(unsigned long clkcon0)519 static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
520 {
521 clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
522
523 return clkcon0 + 1;
524 }
525
526 /* EPLLCON compatible enough to get on/off information */
527
s3c2443_common_setup_clocks(pll_fn get_mpll)528 void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
529 {
530 unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
531 unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
532 unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
533 struct clk *xtal_clk;
534 unsigned long xtal;
535 unsigned long pll;
536 unsigned long fclk;
537 unsigned long hclk;
538 unsigned long pclk;
539 int ptr;
540
541 xtal_clk = clk_get(NULL, "xtal");
542 xtal = clk_get_rate(xtal_clk);
543 clk_put(xtal_clk);
544
545 pll = get_mpll(mpllcon, xtal);
546 clk_msysclk.clk.rate = pll;
547
548 fclk = clk_get_rate(&clk_armdiv);
549 hclk = s3c2443_prediv_getrate(&clk_prediv);
550 hclk /= s3c2443_get_hdiv(clkdiv0);
551 pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
552
553 s3c24xx_setup_clocks(fclk, hclk, pclk);
554
555 printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
556 (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
557 print_mhz(pll), print_mhz(fclk),
558 print_mhz(hclk), print_mhz(pclk));
559
560 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
561 s3c_set_clksrc(&clksrc_clks[ptr], true);
562
563 /* ensure usb bus clock is within correct rate of 48MHz */
564
565 if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) {
566 printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
567 clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000);
568 }
569
570 printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
571 (epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
572 print_mhz(clk_get_rate(&clk_epll)),
573 print_mhz(clk_get_rate(&clk_usb_bus)));
574 }
575
576 static struct clk *clks[] __initdata = {
577 &clk_prediv,
578 &clk_mpllref,
579 &clk_mdivclk,
580 &clk_ext,
581 &clk_epll,
582 &clk_usb_bus,
583 &clk_armdiv,
584 &hsmmc1_clk,
585 };
586
587 static struct clksrc_clk *clksrcs[] __initdata = {
588 &clk_i2s_eplldiv,
589 &clk_i2s,
590 &clk_usb_bus_host,
591 &clk_epllref,
592 &clk_esysclk,
593 &clk_msysclk,
594 &clk_arm,
595 };
596
597 static struct clk_lookup s3c2443_clk_lookup[] = {
598 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
599 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
600 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
601 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
602 };
603
s3c2443_common_init_clocks(int xtal,pll_fn get_mpll,unsigned int * divs,int nr_divs,int divmask)604 void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
605 unsigned int *divs, int nr_divs,
606 int divmask)
607 {
608 int ptr;
609
610 armdiv = divs;
611 nr_armdiv = nr_divs;
612 armdivmask = divmask;
613
614 /* s3c2443 parents h and p clocks from prediv */
615 clk_h.parent = &clk_prediv;
616 clk_p.parent = &clk_prediv;
617
618 clk_usb_bus.parent = &clk_usb_bus_host.clk;
619 clk_epll.parent = &clk_epllref.clk;
620
621 s3c24xx_register_baseclocks(xtal);
622 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
623
624 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
625 s3c_register_clksrc(clksrcs[ptr], 1);
626
627 s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks));
628 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
629
630 /* See s3c2443/etc notes on disabling clocks at init time */
631 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
632 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
633 clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
634
635 s3c2443_common_setup_clocks(get_mpll);
636 }
637