2  * i2sbus driver -- interface register definitions
62  *  - clock source
63  *  - MClk divisor
64  *  - SClk divisor
65  *  - SClk master flag
66  *  - serial format (sony, i2s 64x, i2s 32x, dav, silabs)
67  *  - external sample frequency interrupt (don't understand)
68  *  - external sample frequency
71 /* clock source. You get either 18.432, 45.1584 or 49.1520 MHz */
77 /* also, let's define the exact clock speeds here, in Hz */
81 /* MClk is the clock that drives the codec, usually called its 'system clock'.
82  * It is derived by taking only every 'divisor' tick of the clock.
90 #	define I2S_SF_MCLKDIV_OTHER(div)	(((div/2-1)<<I2S_SF_MCLKDIV_SHIFT)&I2S_SF_MCLKDIV_MASK)  argument
91 static inline int i2s_sf_mclkdiv(int div, int *out)  in i2s_sf_mclkdiv()  argument
95 	switch(div) {  in i2s_sf_mclkdiv()
101 		if (div%2) return -1;  in i2s_sf_mclkdiv()
102 		d = div/2-1;  in i2s_sf_mclkdiv()
104 			return -1;  in i2s_sf_mclkdiv()
105 		*out |= I2S_SF_MCLKDIV_OTHER(div);  in i2s_sf_mclkdiv()
109 /* SClk is the clock that drives the i2s wire bus. Note that it is
117 #	define I2S_SF_SCLKDIV_OTHER(div)	(((div/2-1)<<I2S_SF_SCLKDIV_SHIFT)&I2S_SF_SCLKDIV_MASK)  argument
118 static inline int i2s_sf_sclkdiv(int div, int *out)  in i2s_sf_sclkdiv()  argument
122 	switch(div) {  in i2s_sf_sclkdiv()
126 		if (div%2) return -1;  in i2s_sf_sclkdiv()
127 		d = div/2-1;  in i2s_sf_sclkdiv()
128 		if (d == 8 || d == 9) return -1;  in i2s_sf_sclkdiv()
129 		*out |= I2S_SF_SCLKDIV_OTHER(div);  in i2s_sf_sclkdiv()