Lines Matching +full:clock +full:- +full:div
2 * OMAP3 clock data
4 * Copyright (C) 2007-2010 Texas Instruments, Inc.
5 * Copyright (C) 2007-2011 Nokia Corporation
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
25 #include "clock.h"
32 #include "cm-regbits-34xx.h"
34 #include "prm-regbits-34xx.h"
49 * DPLL1 supplies clock to the MPU.
50 * DPLL2 supplies clock to the IVA2.
62 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
113 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
114 { .div = 0 }
118 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
119 { .div = 0 }
123 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
124 { .div = 0 }
128 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
129 { .div = 0 }
133 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
134 { .div = 0 }
138 { .div = 1, .val = 4, .flags = RATE_IN_3XXX },
139 { .div = 0 }
152 /* Oscillator clock */
166 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
167 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
168 { .div = 0 }
176 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
177 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
194 /* Optional external clock input for some McBSPs */
200 /* PRM EXTERNAL CLOCK OUTPUT */
216 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
217 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
218 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
219 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
220 { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
221 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
222 { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
223 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
224 { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
225 { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
226 { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
227 { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
228 { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
229 { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
230 { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
231 { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
232 { .div = 0 }
236 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
237 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
238 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
239 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
240 { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
241 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
242 { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
243 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
244 { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
245 { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
246 { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
247 { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
248 { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
249 { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
250 { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
251 { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
252 { .div = 17, .val = 17, .flags = RATE_IN_36XX },
253 { .div = 18, .val = 18, .flags = RATE_IN_36XX },
254 { .div = 19, .val = 19, .flags = RATE_IN_36XX },
255 { .div = 20, .val = 20, .flags = RATE_IN_36XX },
256 { .div = 21, .val = 21, .flags = RATE_IN_36XX },
257 { .div = 22, .val = 22, .flags = RATE_IN_36XX },
258 { .div = 23, .val = 23, .flags = RATE_IN_36XX },
259 { .div = 24, .val = 24, .flags = RATE_IN_36XX },
260 { .div = 25, .val = 25, .flags = RATE_IN_36XX },
261 { .div = 26, .val = 26, .flags = RATE_IN_36XX },
262 { .div = 27, .val = 27, .flags = RATE_IN_36XX },
263 { .div = 28, .val = 28, .flags = RATE_IN_36XX },
264 { .div = 29, .val = 29, .flags = RATE_IN_36XX },
265 { .div = 30, .val = 30, .flags = RATE_IN_36XX },
266 { .div = 31, .val = 31, .flags = RATE_IN_36XX },
267 { .div = 32, .val = 32, .flags = RATE_IN_36XX },
268 { .div = 0 }
272 /* MPU clock source */
308 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
326 * Does not exist in the TRM - needed to separate the M2 divider from
342 /* IVA2 clock source */
385 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
403 * Source clock for all interfaces and for some device fclks
404 * REVISIT: Also supports fast relock bypass - not included below
438 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
450 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
451 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
452 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX },
453 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX },
454 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
455 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX },
456 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX },
457 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX },
458 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX },
459 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX },
460 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX },
461 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX },
462 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX },
463 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX },
464 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX },
465 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX },
466 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX },
467 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX },
468 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX },
469 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX },
470 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX },
471 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX },
472 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX },
473 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX },
474 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX },
475 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX },
476 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX },
477 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX },
478 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX },
479 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX },
480 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX },
481 { .div = 0 },
489 /* DPLL3 output M2 - primary control point for CORE speed */
525 /* This virtual clock is the source for dpll3_m3x2_ck */
559 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
621 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
622 * DPLL isn't bypassed --
638 /* This virtual clock is the source for dpll4_m2x2_ck */
670 /* Adding 192MHz Clock node needed by SGX */
679 { .div = 1, .val = 1, .flags = RATE_IN_36XX },
680 { .div = 2, .val = 2, .flags = RATE_IN_36XX },
681 { .div = 0 }
690 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
691 { .div = 0 }
695 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
696 { .div = 0 }
741 /* This virtual clock is the source for dpll4_m3x2_ck */
767 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
768 { .div = 0 }
772 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
773 { .div = 0 }
793 { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
794 { .div = 0 }
798 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
799 { .div = 0 }
826 /* This virtual clock is the source for dpll4_m4x2_ck */
853 /* This virtual clock is the source for dpll4_m5x2_ck */
880 /* This virtual clock is the source for dpll4_m6x2_ck */
914 /* Supplies 120MHz clock, USIM source clock */
967 /* CM EXTERNAL CLOCK OUTPUTS */
970 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
971 { .div = 0 }
975 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
976 { .div = 0 }
980 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
981 { .div = 0 }
985 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
986 { .div = 0 }
1011 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1012 { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1013 { .div = 4, .val = 2, .flags = RATE_IN_3XXX },
1014 { .div = 8, .val = 3, .flags = RATE_IN_3XXX },
1015 { .div = 16, .val = 4, .flags = RATE_IN_3XXX },
1016 { .div = 0 },
1045 /* DPLL power domain clock controls */
1048 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1049 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1050 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1051 { .div = 0 }
1084 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1085 { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1086 { .div = 0 },
1109 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1110 * although it is referenced - so this is a guess
1203 * Virtual parent clock for gfx_l3_ick and gfx_l3_fck
1204 * This interface clock does not have a CM_AUTOIDLE bit
1255 /* SGX power domain - 3430ES2 only */
1258 { .div = 2, .val = 5, .flags = RATE_IN_36XX },
1259 { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
1260 { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
1261 { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
1262 { .div = 0 },
1266 { .div = 1, .val = 4, .flags = RATE_IN_36XX },
1267 { .div = 0 },
1271 { .div = 3, .val = 6, .flags = RATE_IN_36XX },
1272 { .div = 5, .val = 7, .flags = RATE_IN_36XX },
1273 { .div = 0 },
1277 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
1278 { .div = 0 },
1304 /* This interface clock does not have a CM_AUTOIDLE bit */
1418 /* CORE 96M FCLK-derived clocks */
1499 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1500 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1503 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1504 { .div = 0 }
1508 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1509 { .div = 0 }
1544 /* CORE_48M_FCK-derived clocks */
1642 /* DPLL3-derived clock */
1645 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1646 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1647 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
1648 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1649 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
1650 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
1651 { .div = 0 }
1737 /* This interface clock does not have a CM_AUTOIDLE bit */
1806 /* Intersystem Communication Registers - chassis mode only */
2249 /* USBHOST - 3430ES2 only */
2285 { .div = 2, .val = 3, .flags = RATE_IN_3XXX },
2286 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2287 { .div = 8, .val = 5, .flags = RATE_IN_3XXX },
2288 { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
2289 { .div = 0 },
2293 { .div = 4, .val = 7, .flags = RATE_IN_3XXX },
2294 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
2295 { .div = 16, .val = 9, .flags = RATE_IN_3XXX },
2296 { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
2297 { .div = 0 },
2422 /* XXX This clock no longer exists in 3430 TRM rev F */
2445 /* PER clock domain */
2910 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2913 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
2914 { .div = 0 },
2918 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2919 { .div = 0 },
2923 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
2924 { .div = 0 },
2928 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
2929 { .div = 0 },
2941 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2957 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2958 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2959 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2960 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
2961 { .div = 0 },
2981 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2982 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2983 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2984 { .div = 0 },
3031 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
3032 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
3033 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3034 { .div = 0 },
3195 * The UART1/2 functional clock acts as the functional
3196 * clock for UART4. No separate fclk control available.
3230 CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_3XXX),
3231 CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_3XXX),
3232 CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_3XXX),
3233 CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_3XXX),
3234 CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_3XXX),
3301 CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX),
3302 CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX),
3328 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
3329 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3339 CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX),
3340 CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX),
3357 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX),
3358 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX),
3407 CLK("omap-mcbsp.2", "prcm_fck", &per_96m_fck, CK_3XXX),
3408 CLK("omap-mcbsp.3", "prcm_fck", &per_96m_fck, CK_3XXX),
3409 CLK("omap-mcbsp.4", "prcm_fck", &per_96m_fck, CK_3XXX),
3447 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
3448 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
3449 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
3470 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
3471 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
3472 CLK("musb-am35x", "ick", &hsotgusb_ick_am35xx, CK_AM35XX),
3473 CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX),
3512 * test for 3517/3505 :-( in omap3xxx_clk_init()
3540 * has 3430ES2-type clocks. in omap3xxx_clk_init()
3546 WARN(1, "clock: could not identify OMAP3 variant\n"); in omap3xxx_clk_init()
3554 * XXX This type of dynamic rewriting of the clock tree is in omap3xxx_clk_init()
3575 * XXX This type of dynamic rewriting of the clock tree is in omap3xxx_clk_init()
3587 clk_preinit(c->lk.clk); in omap3xxx_clk_init()
3591 if (c->cpu & cpu_clkflg) { in omap3xxx_clk_init()
3592 clkdev_add(&c->lk); in omap3xxx_clk_init()
3593 clk_register(c->lk.clk); in omap3xxx_clk_init()
3594 omap2_init_clk_clkdm(c->lk.clk); in omap3xxx_clk_init()
3613 * Lock DPLL5 -- here only until other device init code can in omap3xxx_clk_init()