Lines Matching +full:clock +full:- +full:div
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
32 #include <mach/clock.h>
35 #include "regs-clkctrl-mx28.h"
52 * DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1
53 * clock pins selected for SAIF1 input clocks.
54 * CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and
55 * SAIF0 clock inputs selected for SAIF1 input clocks.
56 * EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input
58 * EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input
64 return -EINVAL; in mxs_saif_clkmux_select()
80 if (clk->enable_reg) { in _raw_clk_enable()
81 reg = __raw_readl(clk->enable_reg); in _raw_clk_enable()
82 reg &= ~(1 << clk->enable_shift); in _raw_clk_enable()
83 __raw_writel(reg, clk->enable_reg); in _raw_clk_enable()
93 if (clk->enable_reg) { in _raw_clk_disable()
94 reg = __raw_readl(clk->enable_reg); in _raw_clk_disable()
95 reg |= 1 << clk->enable_shift; in _raw_clk_disable()
96 __raw_writel(reg, clk->enable_reg); in _raw_clk_disable()
189 u32 reg, div; \
192 div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f; \
193 parent_rate = clk_get_rate(clk->parent); \
196 div, PARENT_RATE_SHIFT); \
230 return clk_get_rate(clk->parent) / 16; in lradc_clk_get_rate()
236 return clk_get_rate(clk->parent) / 768; in rtc_clk_get_rate()
241 return clk->parent->get_rate(clk->parent) / 750; in clk32k_clk_get_rate()
246 return clk_get_rate(clk->parent) / 4; in spdif_clk_get_rate()
252 u32 reg, div; \
256 if (clk->parent == &ref_xtal_clk) \
257 div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >> \
260 div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >> \
263 if (!div) \
264 return -EINVAL; \
266 return clk_get_rate(clk->parent) / div; \
275 u32 reg, div; \
278 div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV; \
280 if (!div) \
281 return -EINVAL; \
284 return clk_get_rate(clk->parent) >> 16 * div; \
286 return clk_get_rate(clk->parent) / div; \
303 return clk_get_rate(clk->parent); \
323 u32 reg, bm_busy, div_max, d, f, div, frac; \
330 if (clk->parent == &ref_xtal_clk) { \
331 parent_rate = clk_get_rate(clk->parent); \
332 div = DIV_ROUND_UP(parent_rate, rate); \
338 if (div == 0 || div > div_max) \
339 return -EINVAL; \
342 * hack alert: this block modifies clk->parent, too, \
345 parent_rate = clk_get_rate(clk->parent->parent); \
349 div = frac = 1; \
366 if (rate - calc_rate < diff) { \
368 div = d; \
369 diff = rate - calc_rate; \
377 return -EINVAL; \
388 reg |= div << BP_CLKCTRL_CPU_DIV_CPU; \
391 reg |= div << BP_CLKCTRL_##dr##_DIV; \
392 if (reg & (1 << clk->enable_shift)) { \
393 pr_err("%s: clock is gated\n", __func__); \
394 return -EINVAL; \
399 for (i = 10000; i; i--) \
405 return -ETIMEDOUT; \
422 u32 reg, div_max, div; \
426 parent_rate = clk_get_rate(clk->parent); \
429 div = DIV_ROUND_UP(parent_rate, rate); \
430 if (div == 0 || div > div_max) \
431 return -EINVAL; \
435 reg |= div << BP_CLKCTRL_##dr##_DIV; \
436 if (reg & (1 << clk->enable_shift)) { \
437 pr_err("%s: clock is gated\n", __func__); \
438 return -EINVAL; \
442 for (i = 10000; i; i--) \
448 return -ETIMEDOUT; \
456 /* saif clock uses 16 bits frac div */
460 u16 div; \
466 parent_rate = clk_get_rate(clk->parent); \
468 return -EINVAL; \
472 div = (u16)lrate; \
474 if (!div) \
475 return -EINVAL; \
479 reg |= div << BP_CLKCTRL_##rs##_DIV; \
482 for (i = 10000; i; i--) \
488 return -ETIMEDOUT; \
500 return -EINVAL; \
518 if (parent != clk->parent) { \
521 clk->parent = parent; \
541 if (parent != clk->parent) \
542 return -EINVAL; \
642 /* for amba-pl011 driver */
644 _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
645 _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
646 _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
647 _REGISTER_CLOCK("mxs-auart.1", NULL, uart_clk)
648 _REGISTER_CLOCK("mxs-auart.2", NULL, uart_clk)
649 _REGISTER_CLOCK("mxs-auart.3", NULL, uart_clk)
650 _REGISTER_CLOCK("mxs-auart.4", NULL, uart_clk)
653 _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
654 _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
655 _REGISTER_CLOCK("mxs-mmc.0", NULL, ssp0_clk)
656 _REGISTER_CLOCK("mxs-mmc.1", NULL, ssp1_clk)
661 _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
662 _REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk)
663 _REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk)
664 _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
665 _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
666 _REGISTER_CLOCK("mxs-pwm.5", NULL, pwm_clk)
667 _REGISTER_CLOCK("mxs-pwm.6", NULL, pwm_clk)
668 _REGISTER_CLOCK("mxs-pwm.7", NULL, pwm_clk)
671 _REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
672 _REGISTER_CLOCK("mxs-saif.0", NULL, saif0_clk)
673 _REGISTER_CLOCK("mxs-saif.1", NULL, saif1_clk)
704 /* Use int div over frac when both are available */ in clk_misc_init()
740 /* SAIF has to use frac div for functional operation */ in clk_misc_init()
750 * Set safe hbus clock divider. A divider of 3 ensure that in clk_misc_init()
751 * the Vddd voltage required for the cpu clock is sufficiently in clk_misc_init()
752 * high for the hbus clock. in clk_misc_init()
759 for (i = 10000; i; i--) in clk_misc_init()
765 return -ETIMEDOUT; in clk_misc_init()
768 /* Gate off cpu clock in WFI for power saving */ in clk_misc_init()
773 * Extra fec clock setting in clk_misc_init()
774 * The DENX M28 uses an external clock source in clk_misc_init()
775 * and the clock output must not be enabled in clk_misc_init()
785 * 480 MHz seems too high to be ssp clock source directly, in clk_misc_init()
801 * source ssp clock from ref_io0 than ref_xtal, in mx28_clocks_init()
818 * Set an initial clock rate for the saif internal logic to work in mx28_clocks_init()
821 * clock which should be fast enough for the internal logic. in mx28_clocks_init()