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/linux-3.3/Documentation/devicetree/bindings/c6x/
Dinterrupt.txt1 C6X Interrupt Chips
2 -------------------
4 * C64X+ Core Interrupt Controller
6 The core interrupt controller provides 16 prioritized interrupts to the
8 Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
12 --------------------
13 - compatible: Should be "ti,c64x+core-pic";
14 - #interrupt-cells: <1>
16 Interrupt Specifier Definition
17 ------------------------------
[all …]
/linux-3.3/Documentation/devicetree/bindings/
Dmarvell.txt1 Marvell Discovery mv64[345]6x System Controller chips
4 The Marvell mv64[345]60 series of system controller chips contain
7 the system controller chip itself and each of the peripherals
11 1) The /system-controller node
13 This node is used to represent the system-controller and must be
14 present when the system uses a system controller chip. The top-level
15 system-controller node contains information that is global to all
16 devices within the system controller chip. The node name begins
17 with "system-controller" followed by the unit address, which is
18 the base address of the memory-mapped register set for the system
[all …]
Dopen-pic.txt4 representation of an Open PIC compliant interrupt controller. This binding is
13 - compatible: Specifies the compatibility list for the PIC. The type
14 shall be <string> and the value shall include "open-pic".
16 - reg: Specifies the base physical address(s) and size(s) of this
17 PIC's addressable register space. The type shall be <prop-encoded-array>.
19 - interrupt-controller: The presence of this property identifies the node
22 - #interrupt-cells: Specifies the number of cells needed to encode an
23 interrupt source. The type shall be a <u32> and the value shall be 2.
25 - #address-cells: Specifies the number of cells needed to encode an
27 'interrupt-map' nodes do not have to specify a parent unit address.
[all …]
/linux-3.3/Documentation/devicetree/bindings/powerpc/nintendo/
Dwii.txt11 - model : Should be "nintendo,wii"
12 - compatible : Should be "nintendo,wii"
16 This node represents the multi-function "Hollywood" chip, which packages
21 - compatible : Should be "nintendo,hollywood"
30 - compatible : should be "nintendo,hollywood-vi","nintendo,flipper-vi"
31 - reg : should contain the VI registers location and length
32 - interrupts : should contain the VI interrupt
41 - compatible : should be "nintendo,hollywood-pi","nintendo,flipper-pi"
42 - reg : should contain the PI registers location and length
44 1.b.i) The "Flipper" interrupt controller node
[all …]
/linux-3.3/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h2 * Copyright 2007-2010 Analog Devices Inc.
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
12 /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
23 /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
31 /* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
39 #define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */
40 #define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */
41 #define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */
42 #define SIC_ISR0 0xffc00118 /* System Interrupt Status Register 0 */
43 #define SIC_ISR1 0xffc0011c /* System Interrupt Status Register 1 */
[all …]
DdefBF544.h2 * Copyright 2007-2010 Analog Devices Inc.
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
10 /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
13 /* The following are the #defines needed by ADSP-BF544 that are not in the common header */
64 #define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
65 #define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
73 /* CAN Controller 1 Config 1 Registers */
75 #define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Re…
76 #define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Regist…
77 #define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Reg…
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/linux-3.3/Documentation/devicetree/bindings/gpio/
D8xxx_gpio.txt3 This is for the non-QE/CPM/GUTs GPIO controllers as found on
6 Every GPIO controller node must have #gpio-cells property defined,
7 this information will be used to translate gpio-specifiers.
10 - compatible : "fsl,<CHIP>-gpio" followed by "fsl,mpc8349-gpio" for
11 83xx, "fsl,mpc8572-gpio" for 85xx and "fsl,mpc8610-gpio" for 86xx.
12 - #gpio-cells : Should be two. The first cell is the pin number and the
14 - interrupts : Interrupt mapping for GPIO IRQ.
15 - interrupt-parent : Phandle for the interrupt controller that
17 - gpio-controller : Marks the port as GPIO controller.
19 Example of gpio-controller nodes for a MPC8347 SoC:
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/linux-3.3/Documentation/devicetree/bindings/arm/
Dgic.txt1 * ARM Generic Interrupt Controller
8 Secondary GICs are cascaded into the upward interrupt controller and do not
13 - compatible : should be one of:
14 "arm,cortex-a9-gic"
15 "arm,arm11mp-gic"
16 - interrupt-controller : Identifies the node as an interrupt controller
17 - #interrupt-cells : Specifies the number of cells needed to encode an
18 interrupt source. The type shall be a <u32> and the value shall be 3.
20 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
23 The 2nd cell contains the interrupt number for the interrupt type.
[all …]
Dvic.txt1 * ARM Vectored Interrupt Controller
3 One or more Vectored Interrupt Controllers (VIC's) can be connected in an ARM
4 system for interrupt routing. For multiple controllers they can either be
5 nested or have the outputs wire-OR'd together.
9 - compatible : should be one of
10 "arm,pl190-vic"
11 "arm,pl192-vic"
12 - interrupt-controller : Identifies the node as an interrupt controller
13 - #interrupt-cells : The number of cells to define the interrupts. Must be 1 as
14 the VIC has no configuration options for interrupt sources. The cell is a u32
[all …]
/linux-3.3/Documentation/devicetree/bindings/powerpc/fsl/
Dmpic.txt2 Freescale MPIC Interrupt Controller Node
6 The Freescale MPIC interrupt controller is found on all PowerQUICC
9 additional cells in the interrupt specifier defining interrupt type
14 - compatible
22 - reg
24 Value type: <prop-encoded-array>
29 - interrupt-controller
32 Definition: Specifies that this node is an interrupt
33 controller
35 - #interrupt-cells
[all …]
Ddma.txt1 * Freescale 83xx DMA Controller
7 - compatible : compatible list, contains 2 entries, first is
8 "fsl,CHIP-dma", where CHIP is the processor
10 "fsl,elo-dma"
11 - reg : <registers mapping for DMA general status reg>
12 - ranges : Should be defined as specified in 1) to describe the
13 DMA controller channels.
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : <interrupt mapping for DMA IRQ>
16 - interrupt-parent : optional, if needed for interrupt mapping
[all …]
Dmpc5121-psc.txt4 ----------------
7 are specified by fsl,mpc5121-psc-uart nodes in the
8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
9 Controller node fsl,mpc5121-psc-fifo is requered there:
11 fsl,mpc5121-psc-uart nodes
12 --------------------------
15 - compatible : Should contain "fsl,mpc5121-psc-uart" and "fsl,mpc5121-psc"
16 - cell-index : Index of the PSC in hardware
17 - reg : Offset and length of the register set for the PSC device
18 - interrupts : <a b> where a is the interrupt number of the
[all …]
/linux-3.3/arch/arm/mach-at91/include/mach/
Dat91rm9200.h2 * arch/arm/mach-at91/include/mach/at91rm9200.h
22 #define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */
23 #define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */
24 #define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */
25 #define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */
32 #define AT91RM9200_ID_TWI 12 /* Two-Wire Interface */
34 #define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller 0 */
35 #define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller 1 */
36 #define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller 2 */
45 #define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */
[all …]
/linux-3.3/arch/arm/mach-pxa/include/mach/
Dirqs.h2 * arch/arm/mach-pxa/include/mach/irqs.h
25 #define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */
26 #define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI,PXA27x) */
27 #define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI,PXA27x) */
28 #define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */
29 #define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt (PXA27x) */
30 #define IRQ_ACIPC0 PXA_IRQ(5) /* AP-CP Communication (PXA930) */
31 #define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */
33 #define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */
36 #define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */
[all …]
/linux-3.3/arch/arm/mach-bcmring/include/mach/
Dirqs.h17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 /* INTC0 - interrupt controller 0 */
25 #define IRQ_DMA0C0 0 /* DMA0 channel 0 interrupt */
26 #define IRQ_DMA0C1 1 /* DMA0 channel 1 interrupt */
27 #define IRQ_DMA0C2 2 /* DMA0 channel 2 interrupt */
28 #define IRQ_DMA0C3 3 /* DMA0 channel 3 interrupt */
29 #define IRQ_DMA0C4 4 /* DMA0 channel 4 interrupt */
30 #define IRQ_DMA0C5 5 /* DMA0 channel 5 interrupt */
31 #define IRQ_DMA0C6 6 /* DMA0 channel 6 interrupt */
32 #define IRQ_DMA0C7 7 /* DMA0 channel 7 interrupt */
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/linux-3.3/arch/arm/boot/dts/
Dimx53.dtsi9 * http://www.opensource.org/licenses/gpl-license.html
24 tzic: tz-interrupt-controller@0fffc000 {
25 compatible = "fsl,imx53-tzic", "fsl,tzic";
26 interrupt-controller;
27 #interrupt-cells = <1>;
32 #address-cells = <1>;
33 #size-cells = <0>;
36 compatible = "fsl,imx-ckil", "fixed-clock";
37 clock-frequency = <32768>;
41 compatible = "fsl,imx-ckih1", "fixed-clock";
[all …]
Dimx51.dtsi9 * http://www.opensource.org/licenses/gpl-license.html
22 tzic: tz-interrupt-controller@e0000000 {
23 compatible = "fsl,imx51-tzic", "fsl,tzic";
24 interrupt-controller;
25 #interrupt-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
34 compatible = "fsl,imx-ckil", "fixed-clock";
35 clock-frequency = <32768>;
39 compatible = "fsl,imx-ckih1", "fixed-clock";
[all …]
Dpicoxcell-pc3x2.dtsi17 #address-cells = <1>;
18 #size-cells = <1>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "arm,1176jz-s";
26 clock-frequency = <400000000>;
28 d-cache-line-size = <32>;
29 d-cache-size = <32768>;
30 i-cache-line-size = <32>;
31 i-cache-size = <32768>;
[all …]
/linux-3.3/arch/arm/mach-vt8500/include/mach/
Dvt8500_irqs.h2 * arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 /* VT8500 Interrupt Sources */
26 #define IRQ_PATA 3 /* PATA Controller */
28 #define IRQ_DMA 5 /* DMA Controller */
29 #define IRQ_EXT0 6 /* External Interrupt 0 */
30 #define IRQ_EXT1 7 /* External Interrupt 1 */
35 #define IRQ_LCDC 12 /* LCD Controller */
36 #define IRQ_EXT2 13 /* External Interrupt 2 */
37 #define IRQ_EXT3 14 /* External Interrupt 3 */
[all …]
/linux-3.3/arch/c6x/boot/dts/
Dtms320c6457.dtsi3 #address-cells = <1>;
4 #size-cells = <1>;
7 #address-cells = <1>;
8 #size-cells = <0>;
18 compatible = "simple-bus";
20 #address-cells = <1>;
21 #size-cells = <1>;
24 core_pic: interrupt-controller {
25 interrupt-controller;
26 #interrupt-cells = <1>;
[all …]
Dtms320c6474.dtsi3 #address-cells = <1>;
4 #size-cells = <1>;
7 #address-cells = <1>;
8 #size-cells = <0>;
28 compatible = "simple-bus";
30 #address-cells = <1>;
31 #size-cells = <1>;
34 core_pic: interrupt-controller {
35 interrupt-controller;
36 #interrupt-cells = <1>;
[all …]
Dtms320c6455.dtsi3 #address-cells = <1>;
4 #size-cells = <1>;
7 #address-cells = <1>;
8 #size-cells = <0>;
18 compatible = "simple-bus";
20 #address-cells = <1>;
21 #size-cells = <1>;
24 core_pic: interrupt-controller {
25 interrupt-controller;
26 #interrupt-cells = <1>;
[all …]
/linux-3.3/arch/c6x/include/asm/
Dirq.h18 #include <linux/radix-tree.h>
26 * These interrupt vectors are prioritized with IRQ 4 having the highest
31 * feed into one of the 12 general interrupt vectors. The remaining 8 vectors
32 * can each route a single SoC interrupt directly.
41 /* This number is used when no interrupt has been assigned */
44 /* This type is the placeholder for a hardware interrupt number. It has to
50 /* Interrupt controller "host" data structure. This could be defined as a
51 * irq domain controller. That is, it handles the mapping between hardware
52 * and virtual interrupt numbers for a given interrupt domain. The host
59 * we use an open firmware device-tree. We do have references to struct
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/linux-3.3/arch/powerpc/include/asm/
Dirq.h14 #include <linux/radix-tree.h>
26 /* This number is used when no interrupt has been assigned */
30 * no interrupt happened _and_ ignore it (don't count it as bad). Some
33 #define NO_IRQ_IGNORE ((unsigned int)-1)
38 /* Number of irqs reserved for the legacy controller */
44 /* This type is the placeholder for a hardware interrupt number. It has to
50 /* Interrupt controller "host" data structure. This could be defined as a
51 * irq domain controller. That is, it handles the mapping between hardware
52 * and virtual interrupt numbers for a given interrupt domain. The host
59 * we use an open firmware device-tree. We do have references to struct
[all …]
/linux-3.3/arch/arm/mach-bcmring/include/mach/csp/
DintcHw_reg.h2 * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
19 * @brief platform specific interrupt controller bit assignments
29 /* ---- Include Files ---------------------------------------------------- */
34 /* ---- Public Constants and Types --------------------------------------- */
36 #define INTCHW_NUM_IRQ_PER_INTC 32 /* Maximum number of interrupt controllers */
39 /* Defines for interrupt controllers. This simplifies and cleans up the function calls. */
44 /* INTC0 - interrupt controller 0 */
45 #define INTCHW_INTC0_PIF_BITNUM 31 /* Peripheral interface interrupt */
46 #define INTCHW_INTC0_CLCD_BITNUM 30 /* LCD Controller interrupt */
47 #define INTCHW_INTC0_GE_BITNUM 29 /* Graphic engine interrupt */
[all …]

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