Lines Matching +full:interrupt +full:- +full:controller
2 * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
19 * @brief platform specific interrupt controller bit assignments
29 /* ---- Include Files ---------------------------------------------------- */
34 /* ---- Public Constants and Types --------------------------------------- */
36 #define INTCHW_NUM_IRQ_PER_INTC 32 /* Maximum number of interrupt controllers */
39 /* Defines for interrupt controllers. This simplifies and cleans up the function calls. */
44 /* INTC0 - interrupt controller 0 */
45 #define INTCHW_INTC0_PIF_BITNUM 31 /* Peripheral interface interrupt */
46 #define INTCHW_INTC0_CLCD_BITNUM 30 /* LCD Controller interrupt */
47 #define INTCHW_INTC0_GE_BITNUM 29 /* Graphic engine interrupt */
48 #define INTCHW_INTC0_APM_BITNUM 28 /* Audio process module interrupt */
49 #define INTCHW_INTC0_ESW_BITNUM 27 /* Ethernet switch interrupt */
50 #define INTCHW_INTC0_SPIH_BITNUM 26 /* SPI host interrupt */
51 #define INTCHW_INTC0_TIMER3_BITNUM 25 /* Timer3 interrupt */
52 #define INTCHW_INTC0_TIMER2_BITNUM 24 /* Timer2 interrupt */
53 #define INTCHW_INTC0_TIMER1_BITNUM 23 /* Timer1 interrupt */
54 #define INTCHW_INTC0_TIMER0_BITNUM 22 /* Timer0 interrupt */
55 #define INTCHW_INTC0_SDIOH1_BITNUM 21 /* SDIO1 host interrupt */
56 #define INTCHW_INTC0_SDIOH0_BITNUM 20 /* SDIO0 host interrupt */
57 #define INTCHW_INTC0_USBD_BITNUM 19 /* USB device interrupt */
58 #define INTCHW_INTC0_USBH1_BITNUM 18 /* USB1 host interrupt */
59 #define INTCHW_INTC0_USBHD2_BITNUM 17 /* USB host2/device2 interrupt */
60 #define INTCHW_INTC0_VPM_BITNUM 16 /* Voice process module interrupt */
61 #define INTCHW_INTC0_DMA1C7_BITNUM 15 /* DMA1 channel 7 interrupt */
62 #define INTCHW_INTC0_DMA1C6_BITNUM 14 /* DMA1 channel 6 interrupt */
63 #define INTCHW_INTC0_DMA1C5_BITNUM 13 /* DMA1 channel 5 interrupt */
64 #define INTCHW_INTC0_DMA1C4_BITNUM 12 /* DMA1 channel 4 interrupt */
65 #define INTCHW_INTC0_DMA1C3_BITNUM 11 /* DMA1 channel 3 interrupt */
66 #define INTCHW_INTC0_DMA1C2_BITNUM 10 /* DMA1 channel 2 interrupt */
67 #define INTCHW_INTC0_DMA1C1_BITNUM 9 /* DMA1 channel 1 interrupt */
68 #define INTCHW_INTC0_DMA1C0_BITNUM 8 /* DMA1 channel 0 interrupt */
69 #define INTCHW_INTC0_DMA0C7_BITNUM 7 /* DMA0 channel 7 interrupt */
70 #define INTCHW_INTC0_DMA0C6_BITNUM 6 /* DMA0 channel 6 interrupt */
71 #define INTCHW_INTC0_DMA0C5_BITNUM 5 /* DMA0 channel 5 interrupt */
72 #define INTCHW_INTC0_DMA0C4_BITNUM 4 /* DMA0 channel 4 interrupt */
73 #define INTCHW_INTC0_DMA0C3_BITNUM 3 /* DMA0 channel 3 interrupt */
74 #define INTCHW_INTC0_DMA0C2_BITNUM 2 /* DMA0 channel 2 interrupt */
75 #define INTCHW_INTC0_DMA0C1_BITNUM 1 /* DMA0 channel 1 interrupt */
76 #define INTCHW_INTC0_DMA0C0_BITNUM 0 /* DMA0 channel 0 interrupt */
111 /* INTC1 - interrupt controller 1 */
112 #define INTCHW_INTC1_DDRVPMP_BITNUM 27 /* DDR and VPM PLL clock phase relationship interrupt …
113 #define INTCHW_INTC1_DDRVPMT_BITNUM 26 /* DDR and VPM HW phase align timeout interrupt (Not f…
114 #define INTCHW_INTC1_DDRP_BITNUM 26 /* DDR and PLL clock phase relationship interrupt (For…
115 #define INTCHW_INTC1_RTC2_BITNUM 25 /* Real time clock tamper interrupt */
116 #define INTCHW_INTC1_VDEC_BITNUM 24 /* Hantro Video Decoder interrupt */
117 /* Bits 13-23 are non-secure versions of the corresponding secure bits in SINTC bits 0-10. */
118 #define INTCHW_INTC1_SPUM_BITNUM 23 /* Secure process module interrupt */
119 #define INTCHW_INTC1_RTC1_BITNUM 22 /* Real time clock one-shot interrupt */
120 #define INTCHW_INTC1_RTC0_BITNUM 21 /* Real time clock periodic interrupt */
121 #define INTCHW_INTC1_RNG_BITNUM 20 /* Random number generator interrupt */
122 #define INTCHW_INTC1_FMPU_BITNUM 19 /* Flash memory parition unit interrupt */
123 #define INTCHW_INTC1_VMPU_BITNUM 18 /* VRAM memory partition interrupt */
124 #define INTCHW_INTC1_DMPU_BITNUM 17 /* DDR2 memory partition interrupt */
125 #define INTCHW_INTC1_KEYC_BITNUM 16 /* Key pad controller interrupt */
126 #define INTCHW_INTC1_TSC_BITNUM 15 /* Touch screen controller interrupt */
128 #define INTCHW_INTC1_WDOG_BITNUM 13 /* Watchdog timer interrupt */
131 #define INTCHW_INTC1_PMUIRQ_BITNUM 11 /* ARM performance monitor interrupt */
132 #define INTCHW_INTC1_COMMRX_BITNUM 10 /* ARM DDC receive interrupt */
133 #define INTCHW_INTC1_COMMTX_BITNUM 9 /* ARM DDC transmit interrupt */
134 #define INTCHW_INTC1_FLASHC_BITNUM 8 /* Flash controller interrupt */
135 #define INTCHW_INTC1_GPHY_BITNUM 7 /* Gigabit Phy interrupt */
136 #define INTCHW_INTC1_SPIS_BITNUM 6 /* SPI slave interrupt */
137 #define INTCHW_INTC1_I2CS_BITNUM 5 /* I2C slave interrupt */
138 #define INTCHW_INTC1_I2CH_BITNUM 4 /* I2C host interrupt */
139 #define INTCHW_INTC1_I2S1_BITNUM 3 /* I2S1 interrupt */
140 #define INTCHW_INTC1_I2S0_BITNUM 2 /* I2S0 interrupt */
141 #define INTCHW_INTC1_GPIO1_BITNUM 1 /* GPIO bit 64//32 combined interrupt */
142 #define INTCHW_INTC1_GPIO0_BITNUM 0 /* GPIO bit 31//0 combined interrupt */
174 /* SINTC secure int controller */
175 #define INTCHW_SINTC_RTC2_BITNUM 15 /* Real time clock tamper interrupt */
176 #define INTCHW_SINTC_TIMER3_BITNUM 14 /* Secure timer3 interrupt */
177 #define INTCHW_SINTC_TIMER2_BITNUM 13 /* Secure timer2 interrupt */
178 #define INTCHW_SINTC_TIMER1_BITNUM 12 /* Secure timer1 interrupt */
179 #define INTCHW_SINTC_TIMER0_BITNUM 11 /* Secure timer0 interrupt */
180 #define INTCHW_SINTC_SPUM_BITNUM 10 /* Secure process module interrupt */
181 #define INTCHW_SINTC_RTC1_BITNUM 9 /* Real time clock one-shot interrupt */
182 #define INTCHW_SINTC_RTC0_BITNUM 8 /* Real time clock periodic interrupt */
183 #define INTCHW_SINTC_RNG_BITNUM 7 /* Random number generator interrupt */
184 #define INTCHW_SINTC_FMPU_BITNUM 6 /* Flash memory parition unit interrupt */
185 #define INTCHW_SINTC_VMPU_BITNUM 5 /* VRAM memory partition interrupt */
186 #define INTCHW_SINTC_DMPU_BITNUM 4 /* DDR2 memory partition interrupt */
187 #define INTCHW_SINTC_KEYC_BITNUM 3 /* Key pad controller interrupt */
188 #define INTCHW_SINTC_TSC_BITNUM 2 /* Touch screen controller interrupt */
189 #define INTCHW_SINTC_UART0_BITNUM 1 /* UART0 interrupt */
190 #define INTCHW_SINTC_WDOG_BITNUM 0 /* Watchdog timer interrupt */
209 /* PL192 Vectored Interrupt Controller (VIC) layout */
212 #define INTCHW_RAWINTR 0x08 /* Raw Interrupt Status register */
213 #define INTCHW_INTSELECT 0x0c /* Interrupt Select Register */
214 #define INTCHW_INTENABLE 0x10 /* Interrupt Enable Register */
215 #define INTCHW_INTENCLEAR 0x14 /* Interrupt Enable Clear Register */
216 #define INTCHW_SOFTINT 0x18 /* Soft Interrupt Register */
217 #define INTCHW_SOFTINTCLEAR 0x1c /* Soft Interrupt Clear Register */
222 #define INTCHW_VECTPRIO0 0x200 /* Vector Priority Registers 0-31 */
223 #define INTCHW_ADDRESS 0xf00 /* Vector Address Register 0-31 */
224 #define INTCHW_PID 0xfe0 /* Peripheral ID Register 0-3 */
225 #define INTCHW_PCELLID 0xff0 /* PrimeCell ID Register 0-3 */
232 /* ---- Public Variable Externs ------------------------------------------ */
233 /* ---- Public Function Prototypes --------------------------------------- */