bindings/arm/gic.txt

1 * ARM Generic Interrupt Controller
8 Secondary GICs are cascaded into the upward interrupt controller and do not
13 - compatible : should be one of:
14 	"arm,cortex-a9-gic"
15 	"arm,arm11mp-gic"
16 - interrupt-controller : Identifies the node as an interrupt controller
17 - #interrupt-cells : Specifies the number of cells needed to encode an
18   interrupt source.  The type shall be a <u32> and the value shall be 3.
20   The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
23   The 2nd cell contains the interrupt number for the interrupt type.
24   SPI interrupts are in the range [0-987].  PPI interrupts are in the
25   range [0-15].
29 		1 = low-to-high edge triggered
30 		2 = high-to-low edge triggered
31 		4 = active high level-sensitive
32 		8 = active low level-sensitive
33 	bits[15:8] PPI interrupt cpu mask.  Each bit corresponds to each of
35 	the interrupt is wired to that CPU.  Only valid for PPI interrupts.
37 - reg : Specifies base physical address(s) and size of the GIC registers. The
42 - interrupts	: Interrupt source of the parent interrupt controller. Only
45 - cpu-offset	: per-cpu offset within the distributor and cpu interface
47   cpu-offset * cpu-nr.
51 	intc: interrupt-controller@fff11000 {
52 		compatible = "arm,cortex-a9-gic";
53 		#interrupt-cells = <3>;
54 		#address-cells = <1>;
55 		interrupt-controller;