1* ARM Generic Interrupt Controller
2
3ARM SMP cores are often associated with a GIC, providing per processor
4interrupts (PPI), shared processor interrupts (SPI) and software
5generated interrupts (SGI).
6
7Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
8Secondary GICs are cascaded into the upward interrupt controller and do not
9have PPIs or SGIs.
10
11Main node required properties:
12
13- compatible : should be one of:
14	"arm,cortex-a9-gic"
15	"arm,arm11mp-gic"
16- interrupt-controller : Identifies the node as an interrupt controller
17- #interrupt-cells : Specifies the number of cells needed to encode an
18  interrupt source.  The type shall be a <u32> and the value shall be 3.
19
20  The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
21  interrupts.
22
23  The 2nd cell contains the interrupt number for the interrupt type.
24  SPI interrupts are in the range [0-987].  PPI interrupts are in the
25  range [0-15].
26
27  The 3rd cell is the flags, encoded as follows:
28	bits[3:0] trigger type and level flags.
29		1 = low-to-high edge triggered
30		2 = high-to-low edge triggered
31		4 = active high level-sensitive
32		8 = active low level-sensitive
33	bits[15:8] PPI interrupt cpu mask.  Each bit corresponds to each of
34	the 8 possible cpus attached to the GIC.  A bit set to '1' indicated
35	the interrupt is wired to that CPU.  Only valid for PPI interrupts.
36
37- reg : Specifies base physical address(s) and size of the GIC registers. The
38  first region is the GIC distributor register base and size. The 2nd region is
39  the GIC cpu interface register base and size.
40
41Optional
42- interrupts	: Interrupt source of the parent interrupt controller. Only
43  present on secondary GICs.
44
45- cpu-offset	: per-cpu offset within the distributor and cpu interface
46  regions, used when the GIC doesn't have banked registers. The offset is
47  cpu-offset * cpu-nr.
48
49Example:
50
51	intc: interrupt-controller@fff11000 {
52		compatible = "arm,cortex-a9-gic";
53		#interrupt-cells = <3>;
54		#address-cells = <1>;
55		interrupt-controller;
56		reg = <0xfff11000 0x1000>,
57		      <0xfff10100 0x100>;
58	};
59
60