Lines Matching +full:interrupt +full:- +full:controller

2  * arch/arm/mach-at91/include/mach/at91rm9200.h
22 #define AT91RM9200_ID_PIOA	2	/* Parallel IO Controller A */
23 #define AT91RM9200_ID_PIOB	3	/* Parallel IO Controller B */
24 #define AT91RM9200_ID_PIOC	4	/* Parallel IO Controller C */
25 #define AT91RM9200_ID_PIOD	5	/* Parallel IO Controller D */
32 #define AT91RM9200_ID_TWI	12	/* Two-Wire Interface */
34 #define AT91RM9200_ID_SSC0	14	/* Serial Synchronous Controller 0 */
35 #define AT91RM9200_ID_SSC1	15	/* Serial Synchronous Controller 1 */
36 #define AT91RM9200_ID_SSC2	16	/* Serial Synchronous Controller 2 */
45 #define AT91RM9200_ID_IRQ0	25	/* Advanced Interrupt Controller (IRQ0) */
46 #define AT91RM9200_ID_IRQ1	26	/* Advanced Interrupt Controller (IRQ1) */
47 #define AT91RM9200_ID_IRQ2	27	/* Advanced Interrupt Controller (IRQ2) */
48 #define AT91RM9200_ID_IRQ3	28	/* Advanced Interrupt Controller (IRQ3) */
49 #define AT91RM9200_ID_IRQ4	29	/* Advanced Interrupt Controller (IRQ4) */
50 #define AT91RM9200_ID_IRQ5	30	/* Advanced Interrupt Controller (IRQ5) */
51 #define AT91RM9200_ID_IRQ6	31	/* Advanced Interrupt Controller (IRQ6) */
82 #define AT91_PMC	(0xfffffc00 - AT91_BASE_SYS)	/* Power Management Controller */
83 #define AT91_ST		(0xfffffd00 - AT91_BASE_SYS)	/* System Timer */
84 #define AT91_MC		(0xffffff00 - AT91_BASE_SYS)	/* Memory Controllers */
87 #define AT91RM9200_BASE_PIOA	0xfffff400	/* PIO Controller A */
88 #define AT91RM9200_BASE_PIOB	0xfffff600	/* PIO Controller B */
89 #define AT91RM9200_BASE_PIOC	0xfffff800	/* PIO Controller C */
90 #define AT91RM9200_BASE_PIOD	0xfffffa00	/* PIO Controller D */
91 #define AT91RM9200_BASE_RTC	0xfffffe00	/* Real-Time Clock */
109 #define AT91RM9200_UHP_BASE	0x00300000	/* USB Host controller */