powerpc/fsl/mpic.txt

2 Freescale MPIC Interrupt Controller Node
6 The Freescale MPIC interrupt controller is found on all PowerQUICC
9 additional cells in the interrupt specifier defining interrupt type
14   - compatible
22   - reg
24       Value type: <prop-encoded-array>
29   - interrupt-controller
32       Definition: Specifies that this node is an interrupt
33           controller
35   - #interrupt-cells
38       Definition: Shall be 2 or 4.  A value of 2 means that interrupt
39           specifiers do not contain the interrupt-type or type-specific
42   - #address-cells
47   - pic-no-reset
52           the boot program has initialized all interrupt source
53           configuration registers to a sane state-- masked or
57           that any initialization related to interrupt sources shall
60 INTERRUPT SPECIFIER DEFINITION
62   Interrupt specifiers consists of 4 cells encoded as
65    <1st-cell>   interrupt-number
67                 Identifies the interrupt source.  The meaning
68                 depends on the type of interrupt.
70                 Note: If the interrupt-type cell is undefined
71                 (i.e. #interrupt-cells = 2), this cell
73                 interrupt-type 0-- i.e. an external or
74                 normal SoC device interrupt.
76    <2nd-cell>   level-sense information, encoded as follows:
77                     0 = low-to-high edge triggered
78                     1 = active low level-sensitive
79                     2 = active high level-sensitive
80                     3 = high-to-low edge triggered
82    <3rd-cell>   interrupt-type
86                   0 = external or normal SoC device interrupt
88                       The interrupt-number cell contains
89                       the SoC device interrupt number.  The
90                       type-specific cell is undefined.  The
91                       interrupt-number is derived from the
93                       the "Interrupt Source Configuration Registers".
94                       Each source has 32-bytes of registers
96                       region.   So interrupt 0 is at offset 0x0,
97                       interrupt 1 is at offset 0x20, and so on.
99                   1 = error interrupt
101                       The interrupt-number cell contains
102                       the SoC device interrupt number for
103                       the error interrupt.  The type-specific
105                       interrupt number.
107                   2 = MPIC inter-processor interrupt (IPI)
109                       The interrupt-number cell identifies
110                       the MPIC IPI number.  The type-specific
113                   3 = MPIC timer interrupt
115                       The interrupt-number cell identifies
116                       the MPIC timer number.  The type-specific
119    <4th-cell>   type-specific information
121                 The type-specific cell is encoded as follows:
123                  - For interrupt-type 1 (error interrupt),
124                    the type-specific cell contains the
125                    bit number of the error interrupt in the
126                    Error Interrupt Summary Register.
130 	 * mpic interrupt controller with 4 cells per specifier
134 		interrupt-controller;
135 		#interrupt-cells = <4>;
136 		#address-cells = <0>;
142 	 * The MPC8544 I2C controller node has an internal
143 	 * interrupt number of 27.  As per the reference manual
144 	 * this corresponds to interrupt source configuration
147 	 * The interrupt source configuration registers begin
150 	 * To compute the interrupt specifier interrupt number
154 	 * The interrupt source configuration registers begin
159 		#address-cells = <1>;
160 		#size-cells = <0>;
161 		cell-index = <0>;
162 		compatible = "fsl-i2c";
165 		interrupt-parent = <&mpic>;
173 	 *  MPIC IPI interrupts.  Note the interrupt
177 		compatible = "fsl,mpic-ipi";
188 	 *  global timers.  Note the interrupt
192 		compatible = "fsl,mpic-global-timer";
202 	 * Definition of an error interrupt (interrupt type 1).
203 	 * SoC interrupt number is 16 and the specific error
204          * interrupt bit in the error interrupt summary register
207 	memory-controller@8000 {
208 		compatible = "fsl,p4080-memory-controller";