Lines Matching +full:interrupt +full:- +full:controller
2 * Copyright 2007-2010 Analog Devices Inc.
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
12 /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
23 /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
31 /* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
39 #define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */
40 #define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */
41 #define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */
42 #define SIC_ISR0 0xffc00118 /* System Interrupt Status Register 0 */
43 #define SIC_ISR1 0xffc0011c /* System Interrupt Status Register 1 */
44 #define SIC_ISR2 0xffc00120 /* System Interrupt Status Register 2 */
45 #define SIC_IWR0 0xffc00124 /* System Interrupt Wakeup Register 0 */
46 #define SIC_IWR1 0xffc00128 /* System Interrupt Wakeup Register 1 */
47 #define SIC_IWR2 0xffc0012c /* System Interrupt Wakeup Register 2 */
48 #define SIC_IAR0 0xffc00130 /* System Interrupt Assignment Register 0 */
49 #define SIC_IAR1 0xffc00134 /* System Interrupt Assignment Register 1 */
50 #define SIC_IAR2 0xffc00138 /* System Interrupt Assignment Register 2 */
51 #define SIC_IAR3 0xffc0013c /* System Interrupt Assignment Register 3 */
52 #define SIC_IAR4 0xffc00140 /* System Interrupt Assignment Register 4 */
53 #define SIC_IAR5 0xffc00144 /* System Interrupt Assignment Register 5 */
54 #define SIC_IAR6 0xffc00148 /* System Interrupt Assignment Register 6 */
55 #define SIC_IAR7 0xffc0014c /* System Interrupt Assignment Register 7 */
56 #define SIC_IAR8 0xffc00150 /* System Interrupt Assignment Register 8 */
57 #define SIC_IAR9 0xffc00154 /* System Interrupt Assignment Register 9 */
58 #define SIC_IAR10 0xffc00158 /* System Interrupt Assignment Register 10 */
59 #define SIC_IAR11 0xffc0015c /* System Interrupt Assignment Register 11 */
70 #define RTC_ICTL 0xffc00304 /* RTC Interrupt Control Register */
71 #define RTC_ISTAT 0xffc00308 /* RTC Interrupt Status Register */
86 #define UART0_IER_SET 0xffc00420 /* Interrupt Enable Register Set */
87 #define UART0_IER_CLEAR 0xffc00424 /* Interrupt Enable Register Clear */
102 …rs are not defined in the shared file because they are not available on the ADSP-BF542 processor */
115 #define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */
116 #define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */
124 /* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-…
192 #define EBIU_DDRARCT 0xffc00aac /* DDR Auto-refresh Count Register */
202 #define DMAC0_TC_PER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods …
203 #define DMAC0_TC_CNT 0xffc00b10 /* DMA Controller 0 Current Counts Register …
216 #define DMA0_IRQ_STATUS 0xffc00c28 /* DMA Channel 0 Interrupt/Status Register */
232 #define DMA1_IRQ_STATUS 0xffc00c68 /* DMA Channel 1 Interrupt/Status Register */
248 #define DMA2_IRQ_STATUS 0xffc00ca8 /* DMA Channel 2 Interrupt/Status Register */
264 #define DMA3_IRQ_STATUS 0xffc00ce8 /* DMA Channel 3 Interrupt/Status Register */
280 #define DMA4_IRQ_STATUS 0xffc00d28 /* DMA Channel 4 Interrupt/Status Register */
296 #define DMA5_IRQ_STATUS 0xffc00d68 /* DMA Channel 5 Interrupt/Status Register */
312 #define DMA6_IRQ_STATUS 0xffc00da8 /* DMA Channel 6 Interrupt/Status Register */
328 #define DMA7_IRQ_STATUS 0xffc00de8 /* DMA Channel 7 Interrupt/Status Register */
344 #define DMA8_IRQ_STATUS 0xffc00e28 /* DMA Channel 8 Interrupt/Status Register */
360 #define DMA9_IRQ_STATUS 0xffc00e68 /* DMA Channel 9 Interrupt/Status Register */
376 #define DMA10_IRQ_STATUS 0xffc00ea8 /* DMA Channel 10 Interrupt/Status Register …
392 #define DMA11_IRQ_STATUS 0xffc00ee8 /* DMA Channel 11 Interrupt/Status Register …
408 #define MDMA_D0_IRQ_STATUS 0xffc00f28 /* Memory DMA Stream 0 Destination Interrupt…
421 #define MDMA_S0_IRQ_STATUS 0xffc00f68 /* Memory DMA Stream 0 Source Interrupt/Stat…
437 #define MDMA_D1_IRQ_STATUS 0xffc00fa8 /* Memory DMA Stream 1 Destination Interrupt…
450 #define MDMA_S1_IRQ_STATUS 0xffc00fe8 /* Memory DMA Stream 1 Source Interrupt/Stat…
465 #define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */
466 #define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */
487 /* Port Interrupt 0 Registers (32-bit) */
489 #define PINT0_MASK_SET 0xffc01400 /* Pin Interrupt 0 Mask Set Register */
490 #define PINT0_MASK_CLEAR 0xffc01404 /* Pin Interrupt 0 Mask Clear Register */
491 #define PINT0_REQUEST 0xffc01408 /* Pin Interrupt 0 Interrupt Request Registe…
492 #define PINT0_ASSIGN 0xffc0140c /* Pin Interrupt 0 Port Assign Register */
493 #define PINT0_EDGE_SET 0xffc01410 /* Pin Interrupt 0 Edge-sensitivity Set Regi…
494 #define PINT0_EDGE_CLEAR 0xffc01414 /* Pin Interrupt 0 Edge-sensitivity Clear Re…
495 #define PINT0_INVERT_SET 0xffc01418 /* Pin Interrupt 0 Inversion Set Register */
496 #define PINT0_INVERT_CLEAR 0xffc0141c /* Pin Interrupt 0 Inversion Clear Register …
497 #define PINT0_PINSTATE 0xffc01420 /* Pin Interrupt 0 Pin Status Register */
498 #define PINT0_LATCH 0xffc01424 /* Pin Interrupt 0 Latch Register */
500 /* Port Interrupt 1 Registers (32-bit) */
502 #define PINT1_MASK_SET 0xffc01430 /* Pin Interrupt 1 Mask Set Register */
503 #define PINT1_MASK_CLEAR 0xffc01434 /* Pin Interrupt 1 Mask Clear Register */
504 #define PINT1_REQUEST 0xffc01438 /* Pin Interrupt 1 Interrupt Request Registe…
505 #define PINT1_ASSIGN 0xffc0143c /* Pin Interrupt 1 Port Assign Register */
506 #define PINT1_EDGE_SET 0xffc01440 /* Pin Interrupt 1 Edge-sensitivity Set Regi…
507 #define PINT1_EDGE_CLEAR 0xffc01444 /* Pin Interrupt 1 Edge-sensitivity Clear Re…
508 #define PINT1_INVERT_SET 0xffc01448 /* Pin Interrupt 1 Inversion Set Register */
509 #define PINT1_INVERT_CLEAR 0xffc0144c /* Pin Interrupt 1 Inversion Clear Register …
510 #define PINT1_PINSTATE 0xffc01450 /* Pin Interrupt 1 Pin Status Register */
511 #define PINT1_LATCH 0xffc01454 /* Pin Interrupt 1 Latch Register */
513 /* Port Interrupt 2 Registers (32-bit) */
515 #define PINT2_MASK_SET 0xffc01460 /* Pin Interrupt 2 Mask Set Register */
516 #define PINT2_MASK_CLEAR 0xffc01464 /* Pin Interrupt 2 Mask Clear Register */
517 #define PINT2_REQUEST 0xffc01468 /* Pin Interrupt 2 Interrupt Request Registe…
518 #define PINT2_ASSIGN 0xffc0146c /* Pin Interrupt 2 Port Assign Register */
519 #define PINT2_EDGE_SET 0xffc01470 /* Pin Interrupt 2 Edge-sensitivity Set Regi…
520 #define PINT2_EDGE_CLEAR 0xffc01474 /* Pin Interrupt 2 Edge-sensitivity Clear Re…
521 #define PINT2_INVERT_SET 0xffc01478 /* Pin Interrupt 2 Inversion Set Register */
522 #define PINT2_INVERT_CLEAR 0xffc0147c /* Pin Interrupt 2 Inversion Clear Register …
523 #define PINT2_PINSTATE 0xffc01480 /* Pin Interrupt 2 Pin Status Register */
524 #define PINT2_LATCH 0xffc01484 /* Pin Interrupt 2 Latch Register */
526 /* Port Interrupt 3 Registers (32-bit) */
528 #define PINT3_MASK_SET 0xffc01490 /* Pin Interrupt 3 Mask Set Register */
529 #define PINT3_MASK_CLEAR 0xffc01494 /* Pin Interrupt 3 Mask Clear Register */
530 #define PINT3_REQUEST 0xffc01498 /* Pin Interrupt 3 Interrupt Request Registe…
531 #define PINT3_ASSIGN 0xffc0149c /* Pin Interrupt 3 Port Assign Register */
532 #define PINT3_EDGE_SET 0xffc014a0 /* Pin Interrupt 3 Edge-sensitivity Set Regi…
533 #define PINT3_EDGE_CLEAR 0xffc014a4 /* Pin Interrupt 3 Edge-sensitivity Clear Re…
534 #define PINT3_INVERT_SET 0xffc014a8 /* Pin Interrupt 3 Inversion Set Register */
535 #define PINT3_INVERT_CLEAR 0xffc014ac /* Pin Interrupt 3 Inversion Clear Register …
536 #define PINT3_PINSTATE 0xffc014b0 /* Pin Interrupt 3 Pin Status Register */
537 #define PINT3_LATCH 0xffc014b4 /* Pin Interrupt 3 Latch Register */
692 #define DMAC1_TC_PER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods …
693 #define DMAC1_TC_CNT 0xffc01b10 /* DMA Controller 1 Current Counts Register …
706 #define DMA12_IRQ_STATUS 0xffc01c28 /* DMA Channel 12 Interrupt/Status Register …
722 #define DMA13_IRQ_STATUS 0xffc01c68 /* DMA Channel 13 Interrupt/Status Register …
738 #define DMA14_IRQ_STATUS 0xffc01ca8 /* DMA Channel 14 Interrupt/Status Register …
754 #define DMA15_IRQ_STATUS 0xffc01ce8 /* DMA Channel 15 Interrupt/Status Register …
770 #define DMA16_IRQ_STATUS 0xffc01d28 /* DMA Channel 16 Interrupt/Status Register …
786 #define DMA17_IRQ_STATUS 0xffc01d68 /* DMA Channel 17 Interrupt/Status Register …
802 #define DMA18_IRQ_STATUS 0xffc01da8 /* DMA Channel 18 Interrupt/Status Register …
818 #define DMA19_IRQ_STATUS 0xffc01de8 /* DMA Channel 19 Interrupt/Status Register …
834 #define DMA20_IRQ_STATUS 0xffc01e28 /* DMA Channel 20 Interrupt/Status Register …
850 #define DMA21_IRQ_STATUS 0xffc01e68 /* DMA Channel 21 Interrupt/Status Register …
866 #define DMA22_IRQ_STATUS 0xffc01ea8 /* DMA Channel 22 Interrupt/Status Register …
882 #define DMA23_IRQ_STATUS 0xffc01ee8 /* DMA Channel 23 Interrupt/Status Register …
898 #define MDMA_D2_IRQ_STATUS 0xffc01f28 /* Memory DMA Stream 2 Destination Interrupt…
911 #define MDMA_S2_IRQ_STATUS 0xffc01f68 /* Memory DMA Stream 2 Source Interrupt/Stat…
927 #define MDMA_D3_IRQ_STATUS 0xffc01fa8 /* Memory DMA Stream 3 Destination Interrupt…
940 #define MDMA_S3_IRQ_STATUS 0xffc01fe8 /* Memory DMA Stream 3 Source Interrupt/Stat…
955 #define UART1_IER_SET 0xffc02020 /* Interrupt Enable Register Set */
956 #define UART1_IER_CLEAR 0xffc02024 /* Interrupt Enable Register Clear */
960 /* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-B…
1040 /* CAN Controller 0 Config 1 Registers */
1042 #define CAN0_MC1 0xffc02a00 /* CAN Controller 0 Mailbox Configuration Re…
1043 #define CAN0_MD1 0xffc02a04 /* CAN Controller 0 Mailbox Direction Regist…
1044 #define CAN0_TRS1 0xffc02a08 /* CAN Controller 0 Transmit Request Set Reg…
1045 #define CAN0_TRR1 0xffc02a0c /* CAN Controller 0 Transmit Request Reset R…
1046 #define CAN0_TA1 0xffc02a10 /* CAN Controller 0 Transmit Acknowledge Reg…
1047 #define CAN0_AA1 0xffc02a14 /* CAN Controller 0 Abort Acknowledge Regist…
1048 #define CAN0_RMP1 0xffc02a18 /* CAN Controller 0 Receive Message Pending …
1049 #define CAN0_RML1 0xffc02a1c /* CAN Controller 0 Receive Message Lost Reg…
1050 …ne CAN0_MBTIF1 0xffc02a20 /* CAN Controller 0 Mailbox Transmit Interrupt F…
1051 …ne CAN0_MBRIF1 0xffc02a24 /* CAN Controller 0 Mailbox Receive Interrupt Fl…
1052 #define CAN0_MBIM1 0xffc02a28 /* CAN Controller 0 Mailbox Interrupt Mask R…
1053 #define CAN0_RFH1 0xffc02a2c /* CAN Controller 0 Remote Frame Handling En…
1054 #define CAN0_OPSS1 0xffc02a30 /* CAN Controller 0 Overwrite Protection Sin…
1056 /* CAN Controller 0 Config 2 Registers */
1058 #define CAN0_MC2 0xffc02a40 /* CAN Controller 0 Mailbox Configuration Re…
1059 #define CAN0_MD2 0xffc02a44 /* CAN Controller 0 Mailbox Direction Regist…
1060 #define CAN0_TRS2 0xffc02a48 /* CAN Controller 0 Transmit Request Set Reg…
1061 #define CAN0_TRR2 0xffc02a4c /* CAN Controller 0 Transmit Request Reset R…
1062 #define CAN0_TA2 0xffc02a50 /* CAN Controller 0 Transmit Acknowledge Reg…
1063 #define CAN0_AA2 0xffc02a54 /* CAN Controller 0 Abort Acknowledge Regist…
1064 #define CAN0_RMP2 0xffc02a58 /* CAN Controller 0 Receive Message Pending …
1065 #define CAN0_RML2 0xffc02a5c /* CAN Controller 0 Receive Message Lost Reg…
1066 …ne CAN0_MBTIF2 0xffc02a60 /* CAN Controller 0 Mailbox Transmit Interrupt F…
1067 …ne CAN0_MBRIF2 0xffc02a64 /* CAN Controller 0 Mailbox Receive Interrupt Fl…
1068 #define CAN0_MBIM2 0xffc02a68 /* CAN Controller 0 Mailbox Interrupt Mask R…
1069 #define CAN0_RFH2 0xffc02a6c /* CAN Controller 0 Remote Frame Handling En…
1070 #define CAN0_OPSS2 0xffc02a70 /* CAN Controller 0 Overwrite Protection Sin…
1072 /* CAN Controller 0 Clock/Interrupt/Counter Registers */
1074 #define CAN0_CLOCK 0xffc02a80 /* CAN Controller 0 Clock Register */
1075 #define CAN0_TIMING 0xffc02a84 /* CAN Controller 0 Timing Register */
1076 #define CAN0_DEBUG 0xffc02a88 /* CAN Controller 0 Debug Register */
1077 #define CAN0_STATUS 0xffc02a8c /* CAN Controller 0 Global Status Register */
1078 #define CAN0_CEC 0xffc02a90 /* CAN Controller 0 Error Counter Register */
1079 #define CAN0_GIS 0xffc02a94 /* CAN Controller 0 Global Interrupt Status …
1080 #define CAN0_GIM 0xffc02a98 /* CAN Controller 0 Global Interrupt Mask Re…
1081 #define CAN0_GIF 0xffc02a9c /* CAN Controller 0 Global Interrupt Flag Re…
1082 #define CAN0_CONTROL 0xffc02aa0 /* CAN Controller 0 Master Control Register …
1083 #define CAN0_INTR 0xffc02aa4 /* CAN Controller 0 Interrupt Pending Regist…
1084 #define CAN0_MBTD 0xffc02aac /* CAN Controller 0 Mailbox Temporary Disabl…
1085 #define CAN0_EWR 0xffc02ab0 /* CAN Controller 0 Programmable Warning Lev…
1086 #define CAN0_ESR 0xffc02ab4 /* CAN Controller 0 Error Status Register */
1087 #define CAN0_UCCNT 0xffc02ac4 /* CAN Controller 0 Universal Counter Regist…
1088 #define CAN0_UCRC 0xffc02ac8 /* CAN Controller 0 Universal Counter Force …
1089 #define CAN0_UCCNF 0xffc02acc /* CAN Controller 0 Universal Counter Config…
1091 /* CAN Controller 0 Acceptance Registers */
1093 #define CAN0_AM00L 0xffc02b00 /* CAN Controller 0 Mailbox 0 Acceptance Mas…
1094 #define CAN0_AM00H 0xffc02b04 /* CAN Controller 0 Mailbox 0 Acceptance Mas…
1095 #define CAN0_AM01L 0xffc02b08 /* CAN Controller 0 Mailbox 1 Acceptance Mas…
1096 #define CAN0_AM01H 0xffc02b0c /* CAN Controller 0 Mailbox 1 Acceptance Mas…
1097 #define CAN0_AM02L 0xffc02b10 /* CAN Controller 0 Mailbox 2 Acceptance Mas…
1098 #define CAN0_AM02H 0xffc02b14 /* CAN Controller 0 Mailbox 2 Acceptance Mas…
1099 #define CAN0_AM03L 0xffc02b18 /* CAN Controller 0 Mailbox 3 Acceptance Mas…
1100 #define CAN0_AM03H 0xffc02b1c /* CAN Controller 0 Mailbox 3 Acceptance Mas…
1101 #define CAN0_AM04L 0xffc02b20 /* CAN Controller 0 Mailbox 4 Acceptance Mas…
1102 #define CAN0_AM04H 0xffc02b24 /* CAN Controller 0 Mailbox 4 Acceptance Mas…
1103 #define CAN0_AM05L 0xffc02b28 /* CAN Controller 0 Mailbox 5 Acceptance Mas…
1104 #define CAN0_AM05H 0xffc02b2c /* CAN Controller 0 Mailbox 5 Acceptance Mas…
1105 #define CAN0_AM06L 0xffc02b30 /* CAN Controller 0 Mailbox 6 Acceptance Mas…
1106 #define CAN0_AM06H 0xffc02b34 /* CAN Controller 0 Mailbox 6 Acceptance Mas…
1107 #define CAN0_AM07L 0xffc02b38 /* CAN Controller 0 Mailbox 7 Acceptance Mas…
1108 #define CAN0_AM07H 0xffc02b3c /* CAN Controller 0 Mailbox 7 Acceptance Mas…
1109 #define CAN0_AM08L 0xffc02b40 /* CAN Controller 0 Mailbox 8 Acceptance Mas…
1110 #define CAN0_AM08H 0xffc02b44 /* CAN Controller 0 Mailbox 8 Acceptance Mas…
1111 #define CAN0_AM09L 0xffc02b48 /* CAN Controller 0 Mailbox 9 Acceptance Mas…
1112 #define CAN0_AM09H 0xffc02b4c /* CAN Controller 0 Mailbox 9 Acceptance Mas…
1113 #define CAN0_AM10L 0xffc02b50 /* CAN Controller 0 Mailbox 10 Acceptance Ma…
1114 #define CAN0_AM10H 0xffc02b54 /* CAN Controller 0 Mailbox 10 Acceptance Ma…
1115 #define CAN0_AM11L 0xffc02b58 /* CAN Controller 0 Mailbox 11 Acceptance Ma…
1116 #define CAN0_AM11H 0xffc02b5c /* CAN Controller 0 Mailbox 11 Acceptance Ma…
1117 #define CAN0_AM12L 0xffc02b60 /* CAN Controller 0 Mailbox 12 Acceptance Ma…
1118 #define CAN0_AM12H 0xffc02b64 /* CAN Controller 0 Mailbox 12 Acceptance Ma…
1119 #define CAN0_AM13L 0xffc02b68 /* CAN Controller 0 Mailbox 13 Acceptance Ma…
1120 #define CAN0_AM13H 0xffc02b6c /* CAN Controller 0 Mailbox 13 Acceptance Ma…
1121 #define CAN0_AM14L 0xffc02b70 /* CAN Controller 0 Mailbox 14 Acceptance Ma…
1122 #define CAN0_AM14H 0xffc02b74 /* CAN Controller 0 Mailbox 14 Acceptance Ma…
1123 #define CAN0_AM15L 0xffc02b78 /* CAN Controller 0 Mailbox 15 Acceptance Ma…
1124 #define CAN0_AM15H 0xffc02b7c /* CAN Controller 0 Mailbox 15 Acceptance Ma…
1126 /* CAN Controller 0 Acceptance Registers */
1128 #define CAN0_AM16L 0xffc02b80 /* CAN Controller 0 Mailbox 16 Acceptance Ma…
1129 #define CAN0_AM16H 0xffc02b84 /* CAN Controller 0 Mailbox 16 Acceptance Ma…
1130 #define CAN0_AM17L 0xffc02b88 /* CAN Controller 0 Mailbox 17 Acceptance Ma…
1131 #define CAN0_AM17H 0xffc02b8c /* CAN Controller 0 Mailbox 17 Acceptance Ma…
1132 #define CAN0_AM18L 0xffc02b90 /* CAN Controller 0 Mailbox 18 Acceptance Ma…
1133 #define CAN0_AM18H 0xffc02b94 /* CAN Controller 0 Mailbox 18 Acceptance Ma…
1134 #define CAN0_AM19L 0xffc02b98 /* CAN Controller 0 Mailbox 19 Acceptance Ma…
1135 #define CAN0_AM19H 0xffc02b9c /* CAN Controller 0 Mailbox 19 Acceptance Ma…
1136 #define CAN0_AM20L 0xffc02ba0 /* CAN Controller 0 Mailbox 20 Acceptance Ma…
1137 #define CAN0_AM20H 0xffc02ba4 /* CAN Controller 0 Mailbox 20 Acceptance Ma…
1138 #define CAN0_AM21L 0xffc02ba8 /* CAN Controller 0 Mailbox 21 Acceptance Ma…
1139 #define CAN0_AM21H 0xffc02bac /* CAN Controller 0 Mailbox 21 Acceptance Ma…
1140 #define CAN0_AM22L 0xffc02bb0 /* CAN Controller 0 Mailbox 22 Acceptance Ma…
1141 #define CAN0_AM22H 0xffc02bb4 /* CAN Controller 0 Mailbox 22 Acceptance Ma…
1142 #define CAN0_AM23L 0xffc02bb8 /* CAN Controller 0 Mailbox 23 Acceptance Ma…
1143 #define CAN0_AM23H 0xffc02bbc /* CAN Controller 0 Mailbox 23 Acceptance Ma…
1144 #define CAN0_AM24L 0xffc02bc0 /* CAN Controller 0 Mailbox 24 Acceptance Ma…
1145 #define CAN0_AM24H 0xffc02bc4 /* CAN Controller 0 Mailbox 24 Acceptance Ma…
1146 #define CAN0_AM25L 0xffc02bc8 /* CAN Controller 0 Mailbox 25 Acceptance Ma…
1147 #define CAN0_AM25H 0xffc02bcc /* CAN Controller 0 Mailbox 25 Acceptance Ma…
1148 #define CAN0_AM26L 0xffc02bd0 /* CAN Controller 0 Mailbox 26 Acceptance Ma…
1149 #define CAN0_AM26H 0xffc02bd4 /* CAN Controller 0 Mailbox 26 Acceptance Ma…
1150 #define CAN0_AM27L 0xffc02bd8 /* CAN Controller 0 Mailbox 27 Acceptance Ma…
1151 #define CAN0_AM27H 0xffc02bdc /* CAN Controller 0 Mailbox 27 Acceptance Ma…
1152 #define CAN0_AM28L 0xffc02be0 /* CAN Controller 0 Mailbox 28 Acceptance Ma…
1153 #define CAN0_AM28H 0xffc02be4 /* CAN Controller 0 Mailbox 28 Acceptance Ma…
1154 #define CAN0_AM29L 0xffc02be8 /* CAN Controller 0 Mailbox 29 Acceptance Ma…
1155 #define CAN0_AM29H 0xffc02bec /* CAN Controller 0 Mailbox 29 Acceptance Ma…
1156 #define CAN0_AM30L 0xffc02bf0 /* CAN Controller 0 Mailbox 30 Acceptance Ma…
1157 #define CAN0_AM30H 0xffc02bf4 /* CAN Controller 0 Mailbox 30 Acceptance Ma…
1158 #define CAN0_AM31L 0xffc02bf8 /* CAN Controller 0 Mailbox 31 Acceptance Ma…
1159 #define CAN0_AM31H 0xffc02bfc /* CAN Controller 0 Mailbox 31 Acceptance Ma…
1161 /* CAN Controller 0 Mailbox Data Registers */
1163 #define CAN0_MB00_DATA0 0xffc02c00 /* CAN Controller 0 Mailbox 0 Data 0 Registe…
1164 #define CAN0_MB00_DATA1 0xffc02c04 /* CAN Controller 0 Mailbox 0 Data 1 Registe…
1165 #define CAN0_MB00_DATA2 0xffc02c08 /* CAN Controller 0 Mailbox 0 Data 2 Registe…
1166 #define CAN0_MB00_DATA3 0xffc02c0c /* CAN Controller 0 Mailbox 0 Data 3 Registe…
1167 #define CAN0_MB00_LENGTH 0xffc02c10 /* CAN Controller 0 Mailbox 0 Length Registe…
1168 #define CAN0_MB00_TIMESTAMP 0xffc02c14 /* CAN Controller 0 Mailbox 0 Timestamp Regi…
1169 #define CAN0_MB00_ID0 0xffc02c18 /* CAN Controller 0 Mailbox 0 ID0 Register */
1170 #define CAN0_MB00_ID1 0xffc02c1c /* CAN Controller 0 Mailbox 0 ID1 Register */
1171 #define CAN0_MB01_DATA0 0xffc02c20 /* CAN Controller 0 Mailbox 1 Data 0 Registe…
1172 #define CAN0_MB01_DATA1 0xffc02c24 /* CAN Controller 0 Mailbox 1 Data 1 Registe…
1173 #define CAN0_MB01_DATA2 0xffc02c28 /* CAN Controller 0 Mailbox 1 Data 2 Registe…
1174 #define CAN0_MB01_DATA3 0xffc02c2c /* CAN Controller 0 Mailbox 1 Data 3 Registe…
1175 #define CAN0_MB01_LENGTH 0xffc02c30 /* CAN Controller 0 Mailbox 1 Length Registe…
1176 #define CAN0_MB01_TIMESTAMP 0xffc02c34 /* CAN Controller 0 Mailbox 1 Timestamp Regi…
1177 #define CAN0_MB01_ID0 0xffc02c38 /* CAN Controller 0 Mailbox 1 ID0 Register */
1178 #define CAN0_MB01_ID1 0xffc02c3c /* CAN Controller 0 Mailbox 1 ID1 Register */
1179 #define CAN0_MB02_DATA0 0xffc02c40 /* CAN Controller 0 Mailbox 2 Data 0 Registe…
1180 #define CAN0_MB02_DATA1 0xffc02c44 /* CAN Controller 0 Mailbox 2 Data 1 Registe…
1181 #define CAN0_MB02_DATA2 0xffc02c48 /* CAN Controller 0 Mailbox 2 Data 2 Registe…
1182 #define CAN0_MB02_DATA3 0xffc02c4c /* CAN Controller 0 Mailbox 2 Data 3 Registe…
1183 #define CAN0_MB02_LENGTH 0xffc02c50 /* CAN Controller 0 Mailbox 2 Length Registe…
1184 #define CAN0_MB02_TIMESTAMP 0xffc02c54 /* CAN Controller 0 Mailbox 2 Timestamp Regi…
1185 #define CAN0_MB02_ID0 0xffc02c58 /* CAN Controller 0 Mailbox 2 ID0 Register */
1186 #define CAN0_MB02_ID1 0xffc02c5c /* CAN Controller 0 Mailbox 2 ID1 Register */
1187 #define CAN0_MB03_DATA0 0xffc02c60 /* CAN Controller 0 Mailbox 3 Data 0 Registe…
1188 #define CAN0_MB03_DATA1 0xffc02c64 /* CAN Controller 0 Mailbox 3 Data 1 Registe…
1189 #define CAN0_MB03_DATA2 0xffc02c68 /* CAN Controller 0 Mailbox 3 Data 2 Registe…
1190 #define CAN0_MB03_DATA3 0xffc02c6c /* CAN Controller 0 Mailbox 3 Data 3 Registe…
1191 #define CAN0_MB03_LENGTH 0xffc02c70 /* CAN Controller 0 Mailbox 3 Length Registe…
1192 #define CAN0_MB03_TIMESTAMP 0xffc02c74 /* CAN Controller 0 Mailbox 3 Timestamp Regi…
1193 #define CAN0_MB03_ID0 0xffc02c78 /* CAN Controller 0 Mailbox 3 ID0 Register */
1194 #define CAN0_MB03_ID1 0xffc02c7c /* CAN Controller 0 Mailbox 3 ID1 Register */
1195 #define CAN0_MB04_DATA0 0xffc02c80 /* CAN Controller 0 Mailbox 4 Data 0 Registe…
1196 #define CAN0_MB04_DATA1 0xffc02c84 /* CAN Controller 0 Mailbox 4 Data 1 Registe…
1197 #define CAN0_MB04_DATA2 0xffc02c88 /* CAN Controller 0 Mailbox 4 Data 2 Registe…
1198 #define CAN0_MB04_DATA3 0xffc02c8c /* CAN Controller 0 Mailbox 4 Data 3 Registe…
1199 #define CAN0_MB04_LENGTH 0xffc02c90 /* CAN Controller 0 Mailbox 4 Length Registe…
1200 #define CAN0_MB04_TIMESTAMP 0xffc02c94 /* CAN Controller 0 Mailbox 4 Timestamp Regi…
1201 #define CAN0_MB04_ID0 0xffc02c98 /* CAN Controller 0 Mailbox 4 ID0 Register */
1202 #define CAN0_MB04_ID1 0xffc02c9c /* CAN Controller 0 Mailbox 4 ID1 Register */
1203 #define CAN0_MB05_DATA0 0xffc02ca0 /* CAN Controller 0 Mailbox 5 Data 0 Registe…
1204 #define CAN0_MB05_DATA1 0xffc02ca4 /* CAN Controller 0 Mailbox 5 Data 1 Registe…
1205 #define CAN0_MB05_DATA2 0xffc02ca8 /* CAN Controller 0 Mailbox 5 Data 2 Registe…
1206 #define CAN0_MB05_DATA3 0xffc02cac /* CAN Controller 0 Mailbox 5 Data 3 Registe…
1207 #define CAN0_MB05_LENGTH 0xffc02cb0 /* CAN Controller 0 Mailbox 5 Length Registe…
1208 #define CAN0_MB05_TIMESTAMP 0xffc02cb4 /* CAN Controller 0 Mailbox 5 Timestamp Regi…
1209 #define CAN0_MB05_ID0 0xffc02cb8 /* CAN Controller 0 Mailbox 5 ID0 Register */
1210 #define CAN0_MB05_ID1 0xffc02cbc /* CAN Controller 0 Mailbox 5 ID1 Register */
1211 #define CAN0_MB06_DATA0 0xffc02cc0 /* CAN Controller 0 Mailbox 6 Data 0 Registe…
1212 #define CAN0_MB06_DATA1 0xffc02cc4 /* CAN Controller 0 Mailbox 6 Data 1 Registe…
1213 #define CAN0_MB06_DATA2 0xffc02cc8 /* CAN Controller 0 Mailbox 6 Data 2 Registe…
1214 #define CAN0_MB06_DATA3 0xffc02ccc /* CAN Controller 0 Mailbox 6 Data 3 Registe…
1215 #define CAN0_MB06_LENGTH 0xffc02cd0 /* CAN Controller 0 Mailbox 6 Length Registe…
1216 #define CAN0_MB06_TIMESTAMP 0xffc02cd4 /* CAN Controller 0 Mailbox 6 Timestamp Regi…
1217 #define CAN0_MB06_ID0 0xffc02cd8 /* CAN Controller 0 Mailbox 6 ID0 Register */
1218 #define CAN0_MB06_ID1 0xffc02cdc /* CAN Controller 0 Mailbox 6 ID1 Register */
1219 #define CAN0_MB07_DATA0 0xffc02ce0 /* CAN Controller 0 Mailbox 7 Data 0 Registe…
1220 #define CAN0_MB07_DATA1 0xffc02ce4 /* CAN Controller 0 Mailbox 7 Data 1 Registe…
1221 #define CAN0_MB07_DATA2 0xffc02ce8 /* CAN Controller 0 Mailbox 7 Data 2 Registe…
1222 #define CAN0_MB07_DATA3 0xffc02cec /* CAN Controller 0 Mailbox 7 Data 3 Registe…
1223 #define CAN0_MB07_LENGTH 0xffc02cf0 /* CAN Controller 0 Mailbox 7 Length Registe…
1224 #define CAN0_MB07_TIMESTAMP 0xffc02cf4 /* CAN Controller 0 Mailbox 7 Timestamp Regi…
1225 #define CAN0_MB07_ID0 0xffc02cf8 /* CAN Controller 0 Mailbox 7 ID0 Register */
1226 #define CAN0_MB07_ID1 0xffc02cfc /* CAN Controller 0 Mailbox 7 ID1 Register */
1227 #define CAN0_MB08_DATA0 0xffc02d00 /* CAN Controller 0 Mailbox 8 Data 0 Registe…
1228 #define CAN0_MB08_DATA1 0xffc02d04 /* CAN Controller 0 Mailbox 8 Data 1 Registe…
1229 #define CAN0_MB08_DATA2 0xffc02d08 /* CAN Controller 0 Mailbox 8 Data 2 Registe…
1230 #define CAN0_MB08_DATA3 0xffc02d0c /* CAN Controller 0 Mailbox 8 Data 3 Registe…
1231 #define CAN0_MB08_LENGTH 0xffc02d10 /* CAN Controller 0 Mailbox 8 Length Registe…
1232 #define CAN0_MB08_TIMESTAMP 0xffc02d14 /* CAN Controller 0 Mailbox 8 Timestamp Regi…
1233 #define CAN0_MB08_ID0 0xffc02d18 /* CAN Controller 0 Mailbox 8 ID0 Register */
1234 #define CAN0_MB08_ID1 0xffc02d1c /* CAN Controller 0 Mailbox 8 ID1 Register */
1235 #define CAN0_MB09_DATA0 0xffc02d20 /* CAN Controller 0 Mailbox 9 Data 0 Registe…
1236 #define CAN0_MB09_DATA1 0xffc02d24 /* CAN Controller 0 Mailbox 9 Data 1 Registe…
1237 #define CAN0_MB09_DATA2 0xffc02d28 /* CAN Controller 0 Mailbox 9 Data 2 Registe…
1238 #define CAN0_MB09_DATA3 0xffc02d2c /* CAN Controller 0 Mailbox 9 Data 3 Registe…
1239 #define CAN0_MB09_LENGTH 0xffc02d30 /* CAN Controller 0 Mailbox 9 Length Registe…
1240 #define CAN0_MB09_TIMESTAMP 0xffc02d34 /* CAN Controller 0 Mailbox 9 Timestamp Regi…
1241 #define CAN0_MB09_ID0 0xffc02d38 /* CAN Controller 0 Mailbox 9 ID0 Register */
1242 #define CAN0_MB09_ID1 0xffc02d3c /* CAN Controller 0 Mailbox 9 ID1 Register */
1243 #define CAN0_MB10_DATA0 0xffc02d40 /* CAN Controller 0 Mailbox 10 Data 0 Regist…
1244 #define CAN0_MB10_DATA1 0xffc02d44 /* CAN Controller 0 Mailbox 10 Data 1 Regist…
1245 #define CAN0_MB10_DATA2 0xffc02d48 /* CAN Controller 0 Mailbox 10 Data 2 Regist…
1246 #define CAN0_MB10_DATA3 0xffc02d4c /* CAN Controller 0 Mailbox 10 Data 3 Regist…
1247 #define CAN0_MB10_LENGTH 0xffc02d50 /* CAN Controller 0 Mailbox 10 Length Regist…
1248 #define CAN0_MB10_TIMESTAMP 0xffc02d54 /* CAN Controller 0 Mailbox 10 Timestamp Reg…
1249 #define CAN0_MB10_ID0 0xffc02d58 /* CAN Controller 0 Mailbox 10 ID0 Register …
1250 #define CAN0_MB10_ID1 0xffc02d5c /* CAN Controller 0 Mailbox 10 ID1 Register …
1251 #define CAN0_MB11_DATA0 0xffc02d60 /* CAN Controller 0 Mailbox 11 Data 0 Regist…
1252 #define CAN0_MB11_DATA1 0xffc02d64 /* CAN Controller 0 Mailbox 11 Data 1 Regist…
1253 #define CAN0_MB11_DATA2 0xffc02d68 /* CAN Controller 0 Mailbox 11 Data 2 Regist…
1254 #define CAN0_MB11_DATA3 0xffc02d6c /* CAN Controller 0 Mailbox 11 Data 3 Regist…
1255 #define CAN0_MB11_LENGTH 0xffc02d70 /* CAN Controller 0 Mailbox 11 Length Regist…
1256 #define CAN0_MB11_TIMESTAMP 0xffc02d74 /* CAN Controller 0 Mailbox 11 Timestamp Reg…
1257 #define CAN0_MB11_ID0 0xffc02d78 /* CAN Controller 0 Mailbox 11 ID0 Register …
1258 #define CAN0_MB11_ID1 0xffc02d7c /* CAN Controller 0 Mailbox 11 ID1 Register …
1259 #define CAN0_MB12_DATA0 0xffc02d80 /* CAN Controller 0 Mailbox 12 Data 0 Regist…
1260 #define CAN0_MB12_DATA1 0xffc02d84 /* CAN Controller 0 Mailbox 12 Data 1 Regist…
1261 #define CAN0_MB12_DATA2 0xffc02d88 /* CAN Controller 0 Mailbox 12 Data 2 Regist…
1262 #define CAN0_MB12_DATA3 0xffc02d8c /* CAN Controller 0 Mailbox 12 Data 3 Regist…
1263 #define CAN0_MB12_LENGTH 0xffc02d90 /* CAN Controller 0 Mailbox 12 Length Regist…
1264 #define CAN0_MB12_TIMESTAMP 0xffc02d94 /* CAN Controller 0 Mailbox 12 Timestamp Reg…
1265 #define CAN0_MB12_ID0 0xffc02d98 /* CAN Controller 0 Mailbox 12 ID0 Register …
1266 #define CAN0_MB12_ID1 0xffc02d9c /* CAN Controller 0 Mailbox 12 ID1 Register …
1267 #define CAN0_MB13_DATA0 0xffc02da0 /* CAN Controller 0 Mailbox 13 Data 0 Regist…
1268 #define CAN0_MB13_DATA1 0xffc02da4 /* CAN Controller 0 Mailbox 13 Data 1 Regist…
1269 #define CAN0_MB13_DATA2 0xffc02da8 /* CAN Controller 0 Mailbox 13 Data 2 Regist…
1270 #define CAN0_MB13_DATA3 0xffc02dac /* CAN Controller 0 Mailbox 13 Data 3 Regist…
1271 #define CAN0_MB13_LENGTH 0xffc02db0 /* CAN Controller 0 Mailbox 13 Length Regist…
1272 #define CAN0_MB13_TIMESTAMP 0xffc02db4 /* CAN Controller 0 Mailbox 13 Timestamp Reg…
1273 #define CAN0_MB13_ID0 0xffc02db8 /* CAN Controller 0 Mailbox 13 ID0 Register …
1274 #define CAN0_MB13_ID1 0xffc02dbc /* CAN Controller 0 Mailbox 13 ID1 Register …
1275 #define CAN0_MB14_DATA0 0xffc02dc0 /* CAN Controller 0 Mailbox 14 Data 0 Regist…
1276 #define CAN0_MB14_DATA1 0xffc02dc4 /* CAN Controller 0 Mailbox 14 Data 1 Regist…
1277 #define CAN0_MB14_DATA2 0xffc02dc8 /* CAN Controller 0 Mailbox 14 Data 2 Regist…
1278 #define CAN0_MB14_DATA3 0xffc02dcc /* CAN Controller 0 Mailbox 14 Data 3 Regist…
1279 #define CAN0_MB14_LENGTH 0xffc02dd0 /* CAN Controller 0 Mailbox 14 Length Regist…
1280 #define CAN0_MB14_TIMESTAMP 0xffc02dd4 /* CAN Controller 0 Mailbox 14 Timestamp Reg…
1281 #define CAN0_MB14_ID0 0xffc02dd8 /* CAN Controller 0 Mailbox 14 ID0 Register …
1282 #define CAN0_MB14_ID1 0xffc02ddc /* CAN Controller 0 Mailbox 14 ID1 Register …
1283 #define CAN0_MB15_DATA0 0xffc02de0 /* CAN Controller 0 Mailbox 15 Data 0 Regist…
1284 #define CAN0_MB15_DATA1 0xffc02de4 /* CAN Controller 0 Mailbox 15 Data 1 Regist…
1285 #define CAN0_MB15_DATA2 0xffc02de8 /* CAN Controller 0 Mailbox 15 Data 2 Regist…
1286 #define CAN0_MB15_DATA3 0xffc02dec /* CAN Controller 0 Mailbox 15 Data 3 Regist…
1287 #define CAN0_MB15_LENGTH 0xffc02df0 /* CAN Controller 0 Mailbox 15 Length Regist…
1288 #define CAN0_MB15_TIMESTAMP 0xffc02df4 /* CAN Controller 0 Mailbox 15 Timestamp Reg…
1289 #define CAN0_MB15_ID0 0xffc02df8 /* CAN Controller 0 Mailbox 15 ID0 Register …
1290 #define CAN0_MB15_ID1 0xffc02dfc /* CAN Controller 0 Mailbox 15 ID1 Register …
1292 /* CAN Controller 0 Mailbox Data Registers */
1294 #define CAN0_MB16_DATA0 0xffc02e00 /* CAN Controller 0 Mailbox 16 Data 0 Regist…
1295 #define CAN0_MB16_DATA1 0xffc02e04 /* CAN Controller 0 Mailbox 16 Data 1 Regist…
1296 #define CAN0_MB16_DATA2 0xffc02e08 /* CAN Controller 0 Mailbox 16 Data 2 Regist…
1297 #define CAN0_MB16_DATA3 0xffc02e0c /* CAN Controller 0 Mailbox 16 Data 3 Regist…
1298 #define CAN0_MB16_LENGTH 0xffc02e10 /* CAN Controller 0 Mailbox 16 Length Regist…
1299 #define CAN0_MB16_TIMESTAMP 0xffc02e14 /* CAN Controller 0 Mailbox 16 Timestamp Reg…
1300 #define CAN0_MB16_ID0 0xffc02e18 /* CAN Controller 0 Mailbox 16 ID0 Register …
1301 #define CAN0_MB16_ID1 0xffc02e1c /* CAN Controller 0 Mailbox 16 ID1 Register …
1302 #define CAN0_MB17_DATA0 0xffc02e20 /* CAN Controller 0 Mailbox 17 Data 0 Regist…
1303 #define CAN0_MB17_DATA1 0xffc02e24 /* CAN Controller 0 Mailbox 17 Data 1 Regist…
1304 #define CAN0_MB17_DATA2 0xffc02e28 /* CAN Controller 0 Mailbox 17 Data 2 Regist…
1305 #define CAN0_MB17_DATA3 0xffc02e2c /* CAN Controller 0 Mailbox 17 Data 3 Regist…
1306 #define CAN0_MB17_LENGTH 0xffc02e30 /* CAN Controller 0 Mailbox 17 Length Regist…
1307 #define CAN0_MB17_TIMESTAMP 0xffc02e34 /* CAN Controller 0 Mailbox 17 Timestamp Reg…
1308 #define CAN0_MB17_ID0 0xffc02e38 /* CAN Controller 0 Mailbox 17 ID0 Register …
1309 #define CAN0_MB17_ID1 0xffc02e3c /* CAN Controller 0 Mailbox 17 ID1 Register …
1310 #define CAN0_MB18_DATA0 0xffc02e40 /* CAN Controller 0 Mailbox 18 Data 0 Regist…
1311 #define CAN0_MB18_DATA1 0xffc02e44 /* CAN Controller 0 Mailbox 18 Data 1 Regist…
1312 #define CAN0_MB18_DATA2 0xffc02e48 /* CAN Controller 0 Mailbox 18 Data 2 Regist…
1313 #define CAN0_MB18_DATA3 0xffc02e4c /* CAN Controller 0 Mailbox 18 Data 3 Regist…
1314 #define CAN0_MB18_LENGTH 0xffc02e50 /* CAN Controller 0 Mailbox 18 Length Regist…
1315 #define CAN0_MB18_TIMESTAMP 0xffc02e54 /* CAN Controller 0 Mailbox 18 Timestamp Reg…
1316 #define CAN0_MB18_ID0 0xffc02e58 /* CAN Controller 0 Mailbox 18 ID0 Register …
1317 #define CAN0_MB18_ID1 0xffc02e5c /* CAN Controller 0 Mailbox 18 ID1 Register …
1318 #define CAN0_MB19_DATA0 0xffc02e60 /* CAN Controller 0 Mailbox 19 Data 0 Regist…
1319 #define CAN0_MB19_DATA1 0xffc02e64 /* CAN Controller 0 Mailbox 19 Data 1 Regist…
1320 #define CAN0_MB19_DATA2 0xffc02e68 /* CAN Controller 0 Mailbox 19 Data 2 Regist…
1321 #define CAN0_MB19_DATA3 0xffc02e6c /* CAN Controller 0 Mailbox 19 Data 3 Regist…
1322 #define CAN0_MB19_LENGTH 0xffc02e70 /* CAN Controller 0 Mailbox 19 Length Regist…
1323 #define CAN0_MB19_TIMESTAMP 0xffc02e74 /* CAN Controller 0 Mailbox 19 Timestamp Reg…
1324 #define CAN0_MB19_ID0 0xffc02e78 /* CAN Controller 0 Mailbox 19 ID0 Register …
1325 #define CAN0_MB19_ID1 0xffc02e7c /* CAN Controller 0 Mailbox 19 ID1 Register …
1326 #define CAN0_MB20_DATA0 0xffc02e80 /* CAN Controller 0 Mailbox 20 Data 0 Regist…
1327 #define CAN0_MB20_DATA1 0xffc02e84 /* CAN Controller 0 Mailbox 20 Data 1 Regist…
1328 #define CAN0_MB20_DATA2 0xffc02e88 /* CAN Controller 0 Mailbox 20 Data 2 Regist…
1329 #define CAN0_MB20_DATA3 0xffc02e8c /* CAN Controller 0 Mailbox 20 Data 3 Regist…
1330 #define CAN0_MB20_LENGTH 0xffc02e90 /* CAN Controller 0 Mailbox 20 Length Regist…
1331 #define CAN0_MB20_TIMESTAMP 0xffc02e94 /* CAN Controller 0 Mailbox 20 Timestamp Reg…
1332 #define CAN0_MB20_ID0 0xffc02e98 /* CAN Controller 0 Mailbox 20 ID0 Register …
1333 #define CAN0_MB20_ID1 0xffc02e9c /* CAN Controller 0 Mailbox 20 ID1 Register …
1334 #define CAN0_MB21_DATA0 0xffc02ea0 /* CAN Controller 0 Mailbox 21 Data 0 Regist…
1335 #define CAN0_MB21_DATA1 0xffc02ea4 /* CAN Controller 0 Mailbox 21 Data 1 Regist…
1336 #define CAN0_MB21_DATA2 0xffc02ea8 /* CAN Controller 0 Mailbox 21 Data 2 Regist…
1337 #define CAN0_MB21_DATA3 0xffc02eac /* CAN Controller 0 Mailbox 21 Data 3 Regist…
1338 #define CAN0_MB21_LENGTH 0xffc02eb0 /* CAN Controller 0 Mailbox 21 Length Regist…
1339 #define CAN0_MB21_TIMESTAMP 0xffc02eb4 /* CAN Controller 0 Mailbox 21 Timestamp Reg…
1340 #define CAN0_MB21_ID0 0xffc02eb8 /* CAN Controller 0 Mailbox 21 ID0 Register …
1341 #define CAN0_MB21_ID1 0xffc02ebc /* CAN Controller 0 Mailbox 21 ID1 Register …
1342 #define CAN0_MB22_DATA0 0xffc02ec0 /* CAN Controller 0 Mailbox 22 Data 0 Regist…
1343 #define CAN0_MB22_DATA1 0xffc02ec4 /* CAN Controller 0 Mailbox 22 Data 1 Regist…
1344 #define CAN0_MB22_DATA2 0xffc02ec8 /* CAN Controller 0 Mailbox 22 Data 2 Regist…
1345 #define CAN0_MB22_DATA3 0xffc02ecc /* CAN Controller 0 Mailbox 22 Data 3 Regist…
1346 #define CAN0_MB22_LENGTH 0xffc02ed0 /* CAN Controller 0 Mailbox 22 Length Regist…
1347 #define CAN0_MB22_TIMESTAMP 0xffc02ed4 /* CAN Controller 0 Mailbox 22 Timestamp Reg…
1348 #define CAN0_MB22_ID0 0xffc02ed8 /* CAN Controller 0 Mailbox 22 ID0 Register …
1349 #define CAN0_MB22_ID1 0xffc02edc /* CAN Controller 0 Mailbox 22 ID1 Register …
1350 #define CAN0_MB23_DATA0 0xffc02ee0 /* CAN Controller 0 Mailbox 23 Data 0 Regist…
1351 #define CAN0_MB23_DATA1 0xffc02ee4 /* CAN Controller 0 Mailbox 23 Data 1 Regist…
1352 #define CAN0_MB23_DATA2 0xffc02ee8 /* CAN Controller 0 Mailbox 23 Data 2 Regist…
1353 #define CAN0_MB23_DATA3 0xffc02eec /* CAN Controller 0 Mailbox 23 Data 3 Regist…
1354 #define CAN0_MB23_LENGTH 0xffc02ef0 /* CAN Controller 0 Mailbox 23 Length Regist…
1355 #define CAN0_MB23_TIMESTAMP 0xffc02ef4 /* CAN Controller 0 Mailbox 23 Timestamp Reg…
1356 #define CAN0_MB23_ID0 0xffc02ef8 /* CAN Controller 0 Mailbox 23 ID0 Register …
1357 #define CAN0_MB23_ID1 0xffc02efc /* CAN Controller 0 Mailbox 23 ID1 Register …
1358 #define CAN0_MB24_DATA0 0xffc02f00 /* CAN Controller 0 Mailbox 24 Data 0 Regist…
1359 #define CAN0_MB24_DATA1 0xffc02f04 /* CAN Controller 0 Mailbox 24 Data 1 Regist…
1360 #define CAN0_MB24_DATA2 0xffc02f08 /* CAN Controller 0 Mailbox 24 Data 2 Regist…
1361 #define CAN0_MB24_DATA3 0xffc02f0c /* CAN Controller 0 Mailbox 24 Data 3 Regist…
1362 #define CAN0_MB24_LENGTH 0xffc02f10 /* CAN Controller 0 Mailbox 24 Length Regist…
1363 #define CAN0_MB24_TIMESTAMP 0xffc02f14 /* CAN Controller 0 Mailbox 24 Timestamp Reg…
1364 #define CAN0_MB24_ID0 0xffc02f18 /* CAN Controller 0 Mailbox 24 ID0 Register …
1365 #define CAN0_MB24_ID1 0xffc02f1c /* CAN Controller 0 Mailbox 24 ID1 Register …
1366 #define CAN0_MB25_DATA0 0xffc02f20 /* CAN Controller 0 Mailbox 25 Data 0 Regist…
1367 #define CAN0_MB25_DATA1 0xffc02f24 /* CAN Controller 0 Mailbox 25 Data 1 Regist…
1368 #define CAN0_MB25_DATA2 0xffc02f28 /* CAN Controller 0 Mailbox 25 Data 2 Regist…
1369 #define CAN0_MB25_DATA3 0xffc02f2c /* CAN Controller 0 Mailbox 25 Data 3 Regist…
1370 #define CAN0_MB25_LENGTH 0xffc02f30 /* CAN Controller 0 Mailbox 25 Length Regist…
1371 #define CAN0_MB25_TIMESTAMP 0xffc02f34 /* CAN Controller 0 Mailbox 25 Timestamp Reg…
1372 #define CAN0_MB25_ID0 0xffc02f38 /* CAN Controller 0 Mailbox 25 ID0 Register …
1373 #define CAN0_MB25_ID1 0xffc02f3c /* CAN Controller 0 Mailbox 25 ID1 Register …
1374 #define CAN0_MB26_DATA0 0xffc02f40 /* CAN Controller 0 Mailbox 26 Data 0 Regist…
1375 #define CAN0_MB26_DATA1 0xffc02f44 /* CAN Controller 0 Mailbox 26 Data 1 Regist…
1376 #define CAN0_MB26_DATA2 0xffc02f48 /* CAN Controller 0 Mailbox 26 Data 2 Regist…
1377 #define CAN0_MB26_DATA3 0xffc02f4c /* CAN Controller 0 Mailbox 26 Data 3 Regist…
1378 #define CAN0_MB26_LENGTH 0xffc02f50 /* CAN Controller 0 Mailbox 26 Length Regist…
1379 #define CAN0_MB26_TIMESTAMP 0xffc02f54 /* CAN Controller 0 Mailbox 26 Timestamp Reg…
1380 #define CAN0_MB26_ID0 0xffc02f58 /* CAN Controller 0 Mailbox 26 ID0 Register …
1381 #define CAN0_MB26_ID1 0xffc02f5c /* CAN Controller 0 Mailbox 26 ID1 Register …
1382 #define CAN0_MB27_DATA0 0xffc02f60 /* CAN Controller 0 Mailbox 27 Data 0 Regist…
1383 #define CAN0_MB27_DATA1 0xffc02f64 /* CAN Controller 0 Mailbox 27 Data 1 Regist…
1384 #define CAN0_MB27_DATA2 0xffc02f68 /* CAN Controller 0 Mailbox 27 Data 2 Regist…
1385 #define CAN0_MB27_DATA3 0xffc02f6c /* CAN Controller 0 Mailbox 27 Data 3 Regist…
1386 #define CAN0_MB27_LENGTH 0xffc02f70 /* CAN Controller 0 Mailbox 27 Length Regist…
1387 #define CAN0_MB27_TIMESTAMP 0xffc02f74 /* CAN Controller 0 Mailbox 27 Timestamp Reg…
1388 #define CAN0_MB27_ID0 0xffc02f78 /* CAN Controller 0 Mailbox 27 ID0 Register …
1389 #define CAN0_MB27_ID1 0xffc02f7c /* CAN Controller 0 Mailbox 27 ID1 Register …
1390 #define CAN0_MB28_DATA0 0xffc02f80 /* CAN Controller 0 Mailbox 28 Data 0 Regist…
1391 #define CAN0_MB28_DATA1 0xffc02f84 /* CAN Controller 0 Mailbox 28 Data 1 Regist…
1392 #define CAN0_MB28_DATA2 0xffc02f88 /* CAN Controller 0 Mailbox 28 Data 2 Regist…
1393 #define CAN0_MB28_DATA3 0xffc02f8c /* CAN Controller 0 Mailbox 28 Data 3 Regist…
1394 #define CAN0_MB28_LENGTH 0xffc02f90 /* CAN Controller 0 Mailbox 28 Length Regist…
1395 #define CAN0_MB28_TIMESTAMP 0xffc02f94 /* CAN Controller 0 Mailbox 28 Timestamp Reg…
1396 #define CAN0_MB28_ID0 0xffc02f98 /* CAN Controller 0 Mailbox 28 ID0 Register …
1397 #define CAN0_MB28_ID1 0xffc02f9c /* CAN Controller 0 Mailbox 28 ID1 Register …
1398 #define CAN0_MB29_DATA0 0xffc02fa0 /* CAN Controller 0 Mailbox 29 Data 0 Regist…
1399 #define CAN0_MB29_DATA1 0xffc02fa4 /* CAN Controller 0 Mailbox 29 Data 1 Regist…
1400 #define CAN0_MB29_DATA2 0xffc02fa8 /* CAN Controller 0 Mailbox 29 Data 2 Regist…
1401 #define CAN0_MB29_DATA3 0xffc02fac /* CAN Controller 0 Mailbox 29 Data 3 Regist…
1402 #define CAN0_MB29_LENGTH 0xffc02fb0 /* CAN Controller 0 Mailbox 29 Length Regist…
1403 #define CAN0_MB29_TIMESTAMP 0xffc02fb4 /* CAN Controller 0 Mailbox 29 Timestamp Reg…
1404 #define CAN0_MB29_ID0 0xffc02fb8 /* CAN Controller 0 Mailbox 29 ID0 Register …
1405 #define CAN0_MB29_ID1 0xffc02fbc /* CAN Controller 0 Mailbox 29 ID1 Register …
1406 #define CAN0_MB30_DATA0 0xffc02fc0 /* CAN Controller 0 Mailbox 30 Data 0 Regist…
1407 #define CAN0_MB30_DATA1 0xffc02fc4 /* CAN Controller 0 Mailbox 30 Data 1 Regist…
1408 #define CAN0_MB30_DATA2 0xffc02fc8 /* CAN Controller 0 Mailbox 30 Data 2 Regist…
1409 #define CAN0_MB30_DATA3 0xffc02fcc /* CAN Controller 0 Mailbox 30 Data 3 Regist…
1410 #define CAN0_MB30_LENGTH 0xffc02fd0 /* CAN Controller 0 Mailbox 30 Length Regist…
1411 #define CAN0_MB30_TIMESTAMP 0xffc02fd4 /* CAN Controller 0 Mailbox 30 Timestamp Reg…
1412 #define CAN0_MB30_ID0 0xffc02fd8 /* CAN Controller 0 Mailbox 30 ID0 Register …
1413 #define CAN0_MB30_ID1 0xffc02fdc /* CAN Controller 0 Mailbox 30 ID1 Register …
1414 #define CAN0_MB31_DATA0 0xffc02fe0 /* CAN Controller 0 Mailbox 31 Data 0 Regist…
1415 #define CAN0_MB31_DATA1 0xffc02fe4 /* CAN Controller 0 Mailbox 31 Data 1 Regist…
1416 #define CAN0_MB31_DATA2 0xffc02fe8 /* CAN Controller 0 Mailbox 31 Data 2 Regist…
1417 #define CAN0_MB31_DATA3 0xffc02fec /* CAN Controller 0 Mailbox 31 Data 3 Regist…
1418 #define CAN0_MB31_LENGTH 0xffc02ff0 /* CAN Controller 0 Mailbox 31 Length Regist…
1419 #define CAN0_MB31_TIMESTAMP 0xffc02ff4 /* CAN Controller 0 Mailbox 31 Timestamp Reg…
1420 #define CAN0_MB31_ID0 0xffc02ff8 /* CAN Controller 0 Mailbox 31 ID0 Register …
1421 #define CAN0_MB31_ID1 0xffc02ffc /* CAN Controller 0 Mailbox 31 ID1 Register …
1433 #define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */
1434 #define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */
1442 #define NFC_IRQSTAT 0xffc03b08 /* NAND Interrupt Status Register */
1443 #define NFC_IRQMASK 0xffc03b0c /* NAND Interrupt Mask Register */
1460 #define CNT_IMASK 0xffc04204 /* Interrupt Mask Register */
1483 #define DMAC1_PERIMUX 0xffc04340 /* DMA Controller 1 Peripheral Multiplexer R…
1487 #define OTP_DATA0 0xffc04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the …
1488 #define OTP_DATA1 0xffc04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the …
1489 #define OTP_DATA2 0xffc04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the …
1490 #define OTP_DATA3 0xffc0438c /* OTP/Fuse Data (OTP_DATA0-3) accesses the …
1492 /* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 p…
1502 #define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
1503 #define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
1517 #define DMA0_ERR 0x2 /* DMA Controller 0 Error */
1523 #define RTC 0x80 /* Real-Time Clock */
1532 #define PINT0 0x80000 /* Pin Interrupt 0 */
1533 #define PINT1 0x100000 /* Pin Interrupt 1 */
1537 #define DMA1_ERR 0x1000000 /* DMA Controller 1 Error */
1576 #define NFC_ERR 0x10000000 /* Nand Flash Controller Error */
1597 #define USB_INT0 0x800 /* USB Interrupt 0 */
1598 #define USB_INT1 0x1000 /* USB Interrupt 1 */
1599 #define USB_INT2 0x2000 /* USB Interrupt 2 */
1610 #define PINT2 0x40000000 /* Pin Interrupt 2 */
1611 #define PINT3 0x80000000 /* Pin Interrupt 3 */
1636 /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
1710 #define TRFC 0x3c000 /* Auto-refresh command period */
1711 #define TRP 0x3c0000 /* Pre charge-to-active command period */
1712 #define TRAS 0x3c00000 /* Min Active-to-pre charge time */
1713 #define TRC 0x3c000000 /* Active-to-active time */
1722 #define TRCD 0xf /* Active-to-Read/write delay */
1729 #define TWTR 0xf0000000 /* Write-to-read delay */
1758 #define PASR 0x7 /* Partial array self-refresh */
1785 #define SRREQ 0x8 /* Self-refresh request */
1786 #define SRACK 0x10 /* Self-refresh acknowledge */
1809 #define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */
1835 #define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */
1836 #define CARCOUNT 0x40000 /* Clear auto-refresh count */
1842 /* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET…
1861 /* Bit masks for PORTA_MUX - PORTJ_MUX */
1883 #define IB0 0x1 /* Interrupt Bit 0 */
1884 #define IB1 0x2 /* Interrupt Bit 1 */
1885 #define IB2 0x4 /* Interrupt Bit 2 */
1886 #define IB3 0x8 /* Interrupt Bit 3 */
1887 #define IB4 0x10 /* Interrupt Bit 4 */
1888 #define IB5 0x20 /* Interrupt Bit 5 */
1889 #define IB6 0x40 /* Interrupt Bit 6 */
1890 #define IB7 0x80 /* Interrupt Bit 7 */
1891 #define IB8 0x100 /* Interrupt Bit 8 */
1892 #define IB9 0x200 /* Interrupt Bit 9 */
1893 #define IB10 0x400 /* Interrupt Bit 10 */
1894 #define IB11 0x800 /* Interrupt Bit 11 */
1895 #define IB12 0x1000 /* Interrupt Bit 12 */
1896 #define IB13 0x2000 /* Interrupt Bit 13 */
1897 #define IB14 0x4000 /* Interrupt Bit 14 */
1898 #define IB15 0x8000 /* Interrupt Bit 15 */
1905 #define IRQ_ENA 0x10 /* Interrupt Request Enable */
1937 #define TIMIL0 0x1 /* Timer 0 Interrupt */
1938 #define TIMIL1 0x2 /* Timer 1 Interrupt */
1939 #define TIMIL2 0x4 /* Timer 2 Interrupt */
1940 #define TIMIL3 0x8 /* Timer 3 Interrupt */
1949 #define TIMIL4 0x10000 /* Timer 4 Interrupt */
1950 #define TIMIL5 0x20000 /* Timer 5 Interrupt */
1951 #define TIMIL6 0x40000 /* Timer 6 Interrupt */
1952 #define TIMIL7 0x80000 /* Timer 7 Interrupt */
1985 #define NMI 0x4 /* Non Maskable Interrupt */
1993 #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
2029 #define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format …
2031 #define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */
2037 #define DLEN_8 (0 << 15) /* 000 - 8 bits */
2038 #define DLEN_10 (1 << 15) /* 001 - 10 bits */
2039 #define DLEN_12 (2 << 15) /* 010 - 12 bits */
2040 #define DLEN_14 (3 << 15) /* 011 - 14 bits */
2041 #define DLEN_16 (4 << 15) /* 100 - 16 bits */
2042 #define DLEN_18 (5 << 15) /* 101 - 18 bits */
2043 #define DLEN_24 (6 << 15) /* 110 - 24 bits */
2066 /* The TWI bit masks fields are from the ADSP-BF538 */
2129 #define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */
2130 #define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */
2139 #define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */
2140 #define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */
2141 #define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */
2142 #define SOVFM 0x8 /* Slave Overflow Interrupt Mask */
2143 #define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */
2144 #define MERRM 0x20 /* Master Transfer Error Interrupt Mask */
2145 #define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */
2146 #define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */
2161 #define XMTDATA8 0xff /* Transmit FIFO 8-Bit Data */
2165 #define XMTDATA16 0xffff /* Transmit FIFO 16-Bit Data */
2169 #define RCVDATA8 0xff /* Receive FIFO 8-Bit Data */
2173 #define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */
2181 #define BCODE_WAKEUP 0x0000 /* boot according to wake-up condition */