1b59c632 | 27-Feb-2025 |
Vladimir Murzin <vladimir.murzin@arm.com> |
arm64: Add basic MTE test
Test tag storage access and tag mismatch for different MTE modes.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Reviewed-by: Alexandru Elisei <alexandru.elisei@
arm64: Add basic MTE test
Test tag storage access and tag mismatch for different MTE modes.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com> Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
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0cc3a351 | 22-Feb-2025 |
Sean Christopherson <seanjc@google.com> |
lib: Use __ASSEMBLER__ instead of __ASSEMBLY__
Convert all non-x86 #ifdefs from __ASSEMBLY__ to __ASSEMBLER__, and remove all manual __ASSEMBLY__ #defines. __ASSEMBLY_ was inherited blindly from th
lib: Use __ASSEMBLER__ instead of __ASSEMBLY__
Convert all non-x86 #ifdefs from __ASSEMBLY__ to __ASSEMBLER__, and remove all manual __ASSEMBLY__ #defines. __ASSEMBLY_ was inherited blindly from the Linux kernel, and must be manually defined, e.g. through build rules or with the aforementioned explicit #defines in assembly code.
__ASSEMBLER__ on the other hand is automatically defined by the compiler when preprocessing assembly, i.e. doesn't require manually #defines for the code to function correctly.
Ignore x86, as x86 doesn't actually rely on __ASSEMBLY__ at the moment, and is undergoing a parallel cleanup.
Signed-off-by: Sean Christopherson <seanjc@google.com> Reviewed-by: Andrew Jones <andrew.jones@linux.dev> Message-ID: <20250222014526.2302653-1-seanjc@google.com> [thuth: Fix three more occurances in libfdt.h and sbi-tests.h] Signed-off-by: Thomas Huth <thuth@redhat.com>
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0ed2cdf3 | 28-Nov-2024 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
arm64: Fix sve_vl() for build errors
commit 5b9895f8a5d9 ("arm: Fix clang error in sve_vl()") breaks the build with the following compiler version, as the "rdvl" expects a 64bit register.
/tmp/ccGJ
arm64: Fix sve_vl() for build errors
commit 5b9895f8a5d9 ("arm: Fix clang error in sve_vl()") breaks the build with the following compiler version, as the "rdvl" expects a 64bit register.
/tmp/ccGJYtuC.s: Assembler messages: /tmp/ccGJYtuC.s:2165: Error: operand mismatch -- `rdvl w3,#8' /tmp/ccGJYtuC.s:2165: Info: did you mean this? /tmp/ccGJYtuC.s:2165: Info: rdvl x3, #8 make: *** [<builtin>: arm/selftest.o] Error 1 make: *** Waiting for unfinished jobs....
$ aarch64-none-elf-gcc --version aarch64-none-elf-gcc (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16)) 10.2.1 20201103
Fix this by switching to use "unsigned long" variable and restoring the 64bit register for the instruction
Fixes: 5b9895f8a5d9 ("arm: Fix clang error in sve_vl()") Cc: Raghavendra Rao Ananta <rananta@google.com> Cc: Andrew Jones <andrew.jones@linux.dev> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
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5b9895f8 | 23-Oct-2024 |
Raghavendra Rao Ananta <rananta@google.com> |
arm: Fix clang error in sve_vl()
Fix the following clang error in sve_vl():
In file included from arm/selftest.c:16: kvm-unit-tests/lib/asm/processor.h:163:16: error: value size does not match regi
arm: Fix clang error in sve_vl()
Fix the following clang error in sve_vl():
In file included from arm/selftest.c:16: kvm-unit-tests/lib/asm/processor.h:163:16: error: value size does not match register size specified by the constraint and modifier [-Werror,-Wasm-operand-widths] : "=r" (vl)); ^ kvm-unit-tests/lib/asm/processor.h:162:14: note: use constraint modifier "w" "rdvl %0, #8" ^~ %w0 1 error generated.
Fixes: d47d370c8f ("arm: Add test for FPU/SIMD context save/restore") Signed-off-by: Raghavendra Rao Ananta <rananta@google.com> Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
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d47d370c | 12-Apr-2024 |
Subhasish Ghosh <subhasish.ghosh@arm.com> |
arm: Add test for FPU/SIMD context save/restore
Test that the FPU/SIMD registers are saved and restored correctly when context switching CPUs.
In order to test fpu/simd functionality, we need to ma
arm: Add test for FPU/SIMD context save/restore
Test that the FPU/SIMD registers are saved and restored correctly when context switching CPUs.
In order to test fpu/simd functionality, we need to make sure that kvm-unit-tests doesn't generate code that uses the fpu registers, as that might interfere with the test results. Thus make sure we compile the tests with -mgeneral-regs-only.
Signed-off-by: Subhasish Ghosh <subhasish.ghosh@arm.com> [ Added SVE register tests ] Signed-off-by: Joey Gouly <joey.gouly@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> [Removed references to realms.] Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
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1afc6fb7 | 12-Apr-2024 |
Joey Gouly <joey.gouly@arm.com> |
arm64: add ESR_ELx EC.SVE
Add the SVE exception class, so that SVE exceptions are not printed as 'unknown' exceptions.
Signed-off-by: Joey Gouly <joey.gouly@arm.com> Signed-off-by: Suzuki K Poulose
arm64: add ESR_ELx EC.SVE
Add the SVE exception class, so that SVE exceptions are not printed as 'unknown' exceptions.
Signed-off-by: Joey Gouly <joey.gouly@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
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cddb18bc | 12-Apr-2024 |
Alexandru Elisei <alexandru.elisei@arm.com> |
arm64: Expand SMCCC arguments and return values
PSCI uses the SMC Calling Convention (SMCCC) to communicate with the higher level software. PSCI uses at most 4 arguments and expend only one return v
arm64: Expand SMCCC arguments and return values
PSCI uses the SMC Calling Convention (SMCCC) to communicate with the higher level software. PSCI uses at most 4 arguments and expend only one return value. However, SMCCC has provisions for more arguments (upto 17 depending on the SMCCC version) and upto 10 distinct return values.
We are going to be adding tests that make use of it, so add support for the extended number of arguments and return values.
Also rename the SMCCC functions to generic, non-PSCI names, so they can be used for Realm services.
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> Co-developed-by: Joey Gouly <joey.gouly@arm.com> Signed-off-by: Joey Gouly <joey.gouly@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> [Fixed EFI compile error.] Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
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dc0a3a76 | 02-Apr-2024 |
Andrew Jones <andrew.jones@linux.dev> |
arm64: Prepare for LPA2
When checking for supported granules also check for the values which indicate support when LPA2 is implemented.
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Review
arm64: Prepare for LPA2
When checking for supported granules also check for the values which indicate support when LPA2 is implemented.
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
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a8a78d75 | 05-Mar-2024 |
Andrew Jones <andrew.jones@linux.dev> |
treewide: lib/stack: Fix backtrace
We should never pass the result of __builtin_frame_address(0) to another function since the compiler is within its rights to pop the frame to which it points befor
treewide: lib/stack: Fix backtrace
We should never pass the result of __builtin_frame_address(0) to another function since the compiler is within its rights to pop the frame to which it points before making the function call, as may be done for tail calls. Nobody has complained about backtrace(), so likely all compilations have been inlining backtrace_frame(), not dropping the frame on the tail call, or nobody is looking at traces. However, for riscv, when built for EFI, it does drop the frame on the tail call, and it was noticed. Preemptively fix backtrace() for all architectures.
Fixes: 52266791750d ("lib: backtrace printing") Acked-by: Claudio Imbrenda <imbrenda@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
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22944767 | 27-Feb-2024 |
Andrew Jones <andrew.jones@linux.dev> |
arm64: Improve unhandled exception traces
Put the stack trace at the bottom, rather than mixing it with register dumps, and also start the trace from the current PC.
Signed-off-by: Andrew Jones <an
arm64: Improve unhandled exception traces
Put the stack trace at the bottom, rather than mixing it with register dumps, and also start the trace from the current PC.
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
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dfc1fec2 | 24-Sep-2023 |
Andrew Jones <andrew.jones@linux.dev> |
arm/arm64: Move cpumask.h to common lib
RISC-V will also make use of cpumask.h, so move it to the arch-common directory.
Signed-off-by: Andrew Jones <andrew.jones@linux.dev> Reviewed-by: Thomas Hut
arm/arm64: Move cpumask.h to common lib
RISC-V will also make use of cpumask.h, so move it to the arch-common directory.
Signed-off-by: Andrew Jones <andrew.jones@linux.dev> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com>
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117f2690 | 24-Jul-2023 |
Shaoqin Huang <shahuang@redhat.com> |
arm64: Define name for these bits used in SCTLR_EL1
Currently some fields in SCTLR_EL1 don't define a name and directly used in the SCTLR_EL1_RES1, that's not good now since these fields have been f
arm64: Define name for these bits used in SCTLR_EL1
Currently some fields in SCTLR_EL1 don't define a name and directly used in the SCTLR_EL1_RES1, that's not good now since these fields have been functional and have a name.
Delete the SCTLR_EL1_RES1 since these bits are not RES1 if the related feature has been implemented, it's wired to define these bits as RES1. So simply delete the SCTLR_EL1_RES1 and unwind its definition to INIT_SCTLR_MMU_OFF.
According to the ARM DDI 0487J.a, define the name related to these fields.
Suggested-by: Alexandru Elisei <alexandru.elisei@arm.com> Signed-off-by: Shaoqin Huang <shahuang@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
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16bff5db | 24-Jul-2023 |
Shaoqin Huang <shahuang@redhat.com> |
arm64: Use _BITULL() to define SCTLR_EL1 bit fields
Currently the SCTLR_EL1_* is defined by (1 << x), all of them can be replaced by the _BITULL() macro to make the format consistent with the SCTLR_
arm64: Use _BITULL() to define SCTLR_EL1 bit fields
Currently the SCTLR_EL1_* is defined by (1 << x), all of them can be replaced by the _BITULL() macro to make the format consistent with the SCTLR_EL1_RES1 definition.
Signed-off-by: Shaoqin Huang <shahuang@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
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3bb57711 | 28-Jun-2023 |
Nadav Amit <namit@vmware.com> |
arm64: dump stack on bad exception
Upon a bad exception, the stack is rather useful for debugging, splat it out.
Signed-off-by: Nadav Amit <namit@vmware.com> Signed-off-by: Andrew Jones <andrew.jon
arm64: dump stack on bad exception
Upon a bad exception, the stack is rather useful for debugging, splat it out.
Signed-off-by: Nadav Amit <namit@vmware.com> Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
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ecb5e711 | 28-Jun-2023 |
Nadav Amit <namit@vmware.com> |
arm64: stack: update trace stack on exception
Using gdb for backtracing or dumping the stack following an exception is not very helpful as the exact location of the exception is not saved.
Add an a
arm64: stack: update trace stack on exception
Using gdb for backtracing or dumping the stack following an exception is not very helpful as the exact location of the exception is not saved.
Add an additional frame to save the location of the exception.
One delicate point is dealing with the pretty_print_stacks script. When the stack is dumped, the script would not print the right address for the exception address: for every return address it deducts "1" before looking for the instruction location in the code (using addr2line). As a somewhat hacky solution add "1" for the exception address when dumping the stack.
Signed-off-by: Nadav Amit <namit@vmware.com> Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
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d9de8051 | 28-Jun-2023 |
Nadav Amit <namit@vmware.com> |
arm64: enable frame pointer and support stack unwinding
Enable frame pointers for arm64 and perform stack unwinding based on arm64 convention.
Signed-off-by: Nadav Amit <namit@vmware.com> Signed-of
arm64: enable frame pointer and support stack unwinding
Enable frame pointers for arm64 and perform stack unwinding based on arm64 convention.
Signed-off-by: Nadav Amit <namit@vmware.com> Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
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7a84b7b2 | 11-Mar-2022 |
Thomas Huth <thuth@redhat.com> |
arm: Fix typos
Correct typos which were discovered with the "codespell" utility.
Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Andrew Jones <drjones@redhat.com> |
b4667f4c | 11-Oct-2021 |
Andrew Jones <drjones@redhat.com> |
arm64: gic-v3: Avoid NULL dereferences
LPI allocation requires that the redistributors are configured first. It's unlikely that offline cpus have had their redistributors configured, so filter them
arm64: gic-v3: Avoid NULL dereferences
LPI allocation requires that the redistributors are configured first. It's unlikely that offline cpus have had their redistributors configured, so filter them out right away. Also, assert on any cpu, not just the calling cpu, in gicv3_lpi_alloc_tables() when we detect a unit test failed to follow instructions. Improve the assert with a hint message while we're at it.
Cc: Eric Auger <eric.auger@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-Id: <20211011160420.26785-1-drjones@redhat.com> Signed-off-by: Andrew Jones <drjones@redhat.com>
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80e8b3d8 | 10-Jun-2021 |
Cornelia Huck <cohuck@redhat.com> |
header guards: clean up some stragglers
Some headers had been missed during the initial header guard standardization.
Signed-off-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Laurent Vivier <l
header guards: clean up some stragglers
Some headers had been missed during the initial header guard standardization.
Signed-off-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210610135937.94375-2-cohuck@redhat.com>
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16f52ec9 | 09-Jun-2021 |
Cornelia Huck <cohuck@redhat.com> |
arm: unify header guards
The assembler.h files were the only ones not already following the convention.
Signed-off-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: David Hildenbrand <david@redhat
arm: unify header guards
The assembler.h files were the only ones not already following the convention.
Signed-off-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20210609143712.60933-5-cohuck@redhat.com>
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e97e1c82 | 11-Nov-2020 |
Andrew Jones <drjones@redhat.com> |
arm/arm64: mmu: Stop mapping an assumed IO region
By providing a proper ioremap function, we can just rely on devices calling it for each region they need (as they already do) instead of mapping a b
arm/arm64: mmu: Stop mapping an assumed IO region
By providing a proper ioremap function, we can just rely on devices calling it for each region they need (as they already do) instead of mapping a big assumed I/O range. We don't require the MMU to be enabled at the time of the ioremap. In that case, we add the mapping to the identity map anyway. This allows us to call setup_vm after io_init. Why don't we just call setup_vm before io_init, I hear you ask? Well, that's because tests like sieve want to start with the MMU off, later call setup_vm, and all the while have working I/O. Some unit tests are just really demanding...
While at it, ensure we map the I/O regions with XN (execute never), as suggested by Alexandru Elisei.
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com> Tested-by: Alexandru Elisei <alexandru.elisei@arm.com> Signed-off-by: Andrew Jones <drjones@redhat.com>
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a09aa3fb | 25-Mar-2021 |
Andrew Jones <drjones@redhat.com> |
arm64: Output PC load offset on unhandled exceptions
Since for arm64 we can load the unit tests at different addresses, then let's make it easier to debug by calculating the PC offset for the user.
arm64: Output PC load offset on unhandled exceptions
Since for arm64 we can load the unit tests at different addresses, then let's make it easier to debug by calculating the PC offset for the user. The offset can then be directly used when looking at the disassembly of the test's elf file.
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Signed-off-by: Andrew Jones <drjones@redhat.com>
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8425ac5c | 22-Mar-2021 |
Alexandru Elisei <alexandru.elisei@arm.com> |
arm64: Disable TTBR1_EL1 translation table walks
From an architectural point of view, the PE can speculate instruction fetches and data reads at any time when the MMU is enabled using the translatio
arm64: Disable TTBR1_EL1 translation table walks
From an architectural point of view, the PE can speculate instruction fetches and data reads at any time when the MMU is enabled using the translation tables from TTBR0_EL1 and TTBR1_EL1. kvm-unit-tests uses an identity map, and as such it only programs TTBR0_EL1 with a valid table and leaves TTBR1_EL1 unchanged. The reset value for TTBR1_EL1 is UNKNOWN, which means it is possible for the PE to perform reads from memory locations where accesses can cause side effects (like memory-mapped devices) as part of the speculated translation table walk.
So far, this hasn't been a problem, because KVM resets TTBR{0,1}_EL1 to zero, and that address is used for emulation for both qemu and kvmtool and it doesn't point to a real device. However, kvm-unit-tests shouldn't rely on a particular combination of hypervisor and userspace for correctness. Another situation where we can't rely on these assumptions being true is when kvm-unit-tests is run as an EFI app.
To prevent reads from arbitrary addresses, set the TCR_EL1.EPD1 bit to disable speculative translation table walks using TTBR1_EL1.
This is similar to EDK2 commit fafb7e9c110e ("ArmPkg: correct TTBR1_EL1 settings in TCR_EL1"). Also mentioned in that commit is the Cortex-A57 erratum 822227 which impacts the hypervisor, but kvm-unit-tests is protected against it because asm_mmu_enable sets both the TCR_EL1.TG0 and TCR_EL1.TG1 bits when programming the register.
Suggested-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> Signed-off-by: Andrew Jones <drjones@redhat.com>
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10b65ce7 | 22-Mar-2021 |
Alexandru Elisei <alexandru.elisei@arm.com> |
arm64: Configure SCTLR_EL1 at boot
Some fields in SCTLR_EL1 are UNKNOWN at reset and the arm64 boot requirements, as stated by Linux in Documentation/arm64/booting.rst, do not specify a particular v
arm64: Configure SCTLR_EL1 at boot
Some fields in SCTLR_EL1 are UNKNOWN at reset and the arm64 boot requirements, as stated by Linux in Documentation/arm64/booting.rst, do not specify a particular value for all the fields. Do not rely on the good will of the hypervisor and userspace to set SCTLR_EL1 to a sane value (by their definition of sane) and set SCTLR_EL1 explicitely before running setup(). This will ensure that all tests are performed with the hardware set up identically, regardless of the KVM or VMM versions.
Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> Signed-off-by: Andrew Jones <drjones@redhat.com>
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1dd3501a | 22-Mar-2021 |
Alexandru Elisei <alexandru.elisei@arm.com> |
lib: arm64: Consolidate register definitions to sysreg.h
Move system register field definitions to sysreg.h, where the opcodes for system register access are defined, to align ourselves with the Lin
lib: arm64: Consolidate register definitions to sysreg.h
Move system register field definitions to sysreg.h, where the opcodes for system register access are defined, to align ourselves with the Linux kernel. EL2 support, needed for EFI and nested virtualization testing, will require additional register and field definions, and having them in the same place as Linux will make maintenance easier.
Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> Signed-off-by: Andrew Jones <drjones@redhat.com>
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