1 /* 2 * Ripped off from arch/arm64/include/asm/sysreg.h 3 * 4 * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com> 5 * 6 * This work is licensed under the terms of the GNU LGPL, version 2. 7 */ 8 #ifndef _ASMARM64_SYSREG_H_ 9 #define _ASMARM64_SYSREG_H_ 10 11 #define sys_reg(op0, op1, crn, crm, op2) \ 12 ((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5)) 13 14 #ifdef __ASSEMBLY__ 15 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 16 .equ .L__reg_num_x\num, \num 17 .endr 18 .equ .L__reg_num_xzr, 31 19 20 .macro mrs_s, rt, sreg 21 .inst 0xd5200000|(\sreg)|(.L__reg_num_\rt) 22 .endm 23 24 .macro msr_s, sreg, rt 25 .inst 0xd5000000|(\sreg)|(.L__reg_num_\rt) 26 .endm 27 #else 28 #include <libcflat.h> 29 30 #define read_sysreg(r) ({ \ 31 u64 __val; \ 32 asm volatile("mrs %0, " xstr(r) : "=r" (__val)); \ 33 __val; \ 34 }) 35 36 #define write_sysreg(v, r) do { \ 37 u64 __val = (u64)v; \ 38 asm volatile("msr " xstr(r) ", %x0" : : "rZ" (__val)); \ 39 } while (0) 40 41 #define read_sysreg_s(r) ({ \ 42 u64 __val; \ 43 asm volatile("mrs_s %0, " xstr(r) : "=r" (__val)); \ 44 __val; \ 45 }) 46 47 #define write_sysreg_s(v, r) do { \ 48 u64 __val = (u64)v; \ 49 asm volatile("msr_s " xstr(r) ", %x0" : : "rZ" (__val));\ 50 } while (0) 51 52 #define write_regn_el0(__reg, __n, __val) \ 53 write_sysreg((__val), __reg ## __n ## _el0) 54 55 #define read_regn_el0(__reg, __n) \ 56 read_sysreg(__reg ## __n ## _el0) 57 58 asm( 59 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" 60 " .equ .L__reg_num_x\\num, \\num\n" 61 " .endr\n" 62 " .equ .L__reg_num_xzr, 31\n" 63 "\n" 64 " .macro mrs_s, rt, sreg\n" 65 " .inst 0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n" 66 " .endm\n" 67 "\n" 68 " .macro msr_s, sreg, rt\n" 69 " .inst 0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n" 70 " .endm\n" 71 ); 72 #endif /* __ASSEMBLY__ */ 73 74 #define ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 75 #define ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) 76 #define ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) 77 #define ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) 78 #define ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) 79 80 /* System Control Register (SCTLR_EL1) bits */ 81 #define SCTLR_EL1_EE (1 << 25) 82 #define SCTLR_EL1_WXN (1 << 19) 83 #define SCTLR_EL1_I (1 << 12) 84 #define SCTLR_EL1_SA0 (1 << 4) 85 #define SCTLR_EL1_SA (1 << 3) 86 #define SCTLR_EL1_C (1 << 2) 87 #define SCTLR_EL1_A (1 << 1) 88 #define SCTLR_EL1_M (1 << 0) 89 90 #endif /* _ASMARM64_SYSREG_H_ */ 91