1 #ifndef _X86_MSR_H_ 2 #define _X86_MSR_H_ 3 4 /* CPU model specific register (MSR) numbers */ 5 6 /* x86-64 specific MSRs */ 7 #define MSR_EFER 0xc0000080 /* extended feature register */ 8 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 9 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 10 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 11 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 12 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 13 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 14 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 15 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 16 17 /* EFER bits: */ 18 #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 19 #define _EFER_LME 8 /* Long mode enable */ 20 #define _EFER_LMA 10 /* Long mode active (read-only) */ 21 #define _EFER_NX 11 /* No execute enable */ 22 #define _EFER_SVME 12 /* Enable virtualization */ 23 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 24 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 25 26 #define EFER_SCE (1<<_EFER_SCE) 27 #define EFER_LME (1<<_EFER_LME) 28 #define EFER_LMA (1<<_EFER_LMA) 29 #define EFER_NX (1<<_EFER_NX) 30 #define EFER_SVME (1<<_EFER_SVME) 31 #define EFER_LMSLE (1<<_EFER_LMSLE) 32 #define EFER_FFXSR (1<<_EFER_FFXSR) 33 34 /* Intel MSRs. Some also available on other CPUs */ 35 #define MSR_IA32_SPEC_CTRL 0x00000048 36 #define MSR_IA32_PRED_CMD 0x00000049 37 #define PRED_CMD_IBPB BIT(0) 38 39 #define MSR_IA32_FLUSH_CMD 0x0000010b 40 #define L1D_FLUSH BIT(0) 41 42 #define MSR_IA32_PMC0 0x000004c1 43 #define MSR_IA32_PERFCTR0 0x000000c1 44 #define MSR_IA32_PERFCTR1 0x000000c2 45 #define MSR_FSB_FREQ 0x000000cd 46 47 #define MSR_MTRRcap 0x000000fe 48 #define MSR_IA32_BBL_CR_CTL 0x00000119 49 50 #define MSR_IA32_SYSENTER_CS 0x00000174 51 #define MSR_IA32_SYSENTER_ESP 0x00000175 52 #define MSR_IA32_SYSENTER_EIP 0x00000176 53 54 #define MSR_IA32_MCG_CAP 0x00000179 55 #define MSR_IA32_MCG_STATUS 0x0000017a 56 #define MSR_IA32_MCG_CTL 0x0000017b 57 58 #define MSR_IA32_PEBS_ENABLE 0x000003f1 59 #define MSR_PEBS_DATA_CFG 0x000003f2 60 #define MSR_IA32_DS_AREA 0x00000600 61 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 62 63 #define MSR_MTRRfix64K_00000 0x00000250 64 #define MSR_MTRRfix16K_80000 0x00000258 65 #define MSR_MTRRfix16K_A0000 0x00000259 66 #define MSR_MTRRfix4K_C0000 0x00000268 67 #define MSR_MTRRfix4K_C8000 0x00000269 68 #define MSR_MTRRfix4K_D0000 0x0000026a 69 #define MSR_MTRRfix4K_D8000 0x0000026b 70 #define MSR_MTRRfix4K_E0000 0x0000026c 71 #define MSR_MTRRfix4K_E8000 0x0000026d 72 #define MSR_MTRRfix4K_F0000 0x0000026e 73 #define MSR_MTRRfix4K_F8000 0x0000026f 74 #define MSR_MTRRdefType 0x000002ff 75 76 #define MSR_IA32_CR_PAT 0x00000277 77 78 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 79 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 80 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 81 #define MSR_IA32_LASTINTFROMIP 0x000001dd 82 #define MSR_IA32_LASTINTTOIP 0x000001de 83 84 /* Yes, AMD does indeed record mispredict info in the LBR records themselves. */ 85 #define AMD_LBR_RECORD_MISPREDICT BIT_ULL(63) 86 87 #define LBR_INFO_MISPRED BIT_ULL(63) 88 #define LBR_INFO_IN_TX BIT_ULL(62) 89 #define LBR_INFO_ABORT BIT_ULL(61) 90 #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60) 91 #define LBR_INFO_CYCLES 0xffff 92 #define LBR_INFO_BR_TYPE_OFFSET 56 93 #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) 94 95 /* DEBUGCTLMSR bits (others vary by model): */ 96 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 97 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 98 #define DEBUGCTLMSR_TR (1UL << 6) 99 #define DEBUGCTLMSR_BTS (1UL << 7) 100 #define DEBUGCTLMSR_BTINT (1UL << 8) 101 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 102 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 103 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 104 105 #define MSR_LBR_NHM_FROM 0x00000680 106 #define MSR_LBR_NHM_TO 0x000006c0 107 #define MSR_LBR_CORE_FROM 0x00000040 108 #define MSR_LBR_CORE_TO 0x00000060 109 #define MSR_LBR_TOS 0x000001c9 110 #define MSR_LBR_SELECT 0x000001c8 111 112 #define MSR_IA32_MC0_CTL 0x00000400 113 #define MSR_IA32_MC0_STATUS 0x00000401 114 #define MSR_IA32_MC0_ADDR 0x00000402 115 #define MSR_IA32_MC0_MISC 0x00000403 116 117 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 118 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 119 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 120 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 121 122 /* These are consecutive and not in the normal 4er MCE bank block */ 123 #define MSR_IA32_MC0_CTL2 0x00000280 124 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 125 126 #define CMCI_EN (1ULL << 30) 127 #define CMCI_THRESHOLD_MASK 0xffffULL 128 129 #define MSR_P6_PERFCTR0 0x000000c1 130 #define MSR_P6_PERFCTR1 0x000000c2 131 #define MSR_P6_EVNTSEL0 0x00000186 132 #define MSR_P6_EVNTSEL1 0x00000187 133 134 /* AMD64 MSRs. Not complete. See the architecture manual for a more 135 complete list. */ 136 137 #define MSR_AMD64_PATCH_LEVEL 0x0000008b 138 #define MSR_AMD64_NB_CFG 0xc001001f 139 #define MSR_AMD64_PATCH_LOADER 0xc0010020 140 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 141 #define MSR_AMD64_OSVW_STATUS 0xc0010141 142 #define MSR_AMD64_DC_CFG 0xc0011022 143 #define MSR_AMD64_IBSFETCHCTL 0xc0011030 144 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 145 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 146 #define MSR_AMD64_IBSOPCTL 0xc0011033 147 #define MSR_AMD64_IBSOPRIP 0xc0011034 148 #define MSR_AMD64_IBSOPDATA 0xc0011035 149 #define MSR_AMD64_IBSOPDATA2 0xc0011036 150 #define MSR_AMD64_IBSOPDATA3 0xc0011037 151 #define MSR_AMD64_IBSDCLINAD 0xc0011038 152 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 153 #define MSR_AMD64_IBSCTL 0xc001103a 154 155 /* Fam 10h MSRs */ 156 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 157 #define FAM10H_MMIO_CONF_ENABLE (1<<0) 158 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 159 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 160 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffff 161 #define FAM10H_MMIO_CONF_BASE_SHIFT 20 162 #define MSR_FAM10H_NODE_ID 0xc001100c 163 164 /* Fam 15h MSRs */ 165 #define MSR_F15H_PERF_CTL 0xc0010200 166 #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 167 #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 168 #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 169 #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 170 #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 171 #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 172 173 #define MSR_F15H_PERF_CTR 0xc0010201 174 #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 175 #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 176 #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 177 #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 178 #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 179 #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 180 181 /* K8 MSRs */ 182 #define MSR_K8_TOP_MEM1 0xc001001a 183 #define MSR_K8_TOP_MEM2 0xc001001d 184 #define MSR_K8_SYSCFG 0xc0010010 185 #define MSR_K8_INT_PENDING_MSG 0xc0010055 186 /* C1E active bits in int pending message */ 187 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 188 #define MSR_K8_TSEG_ADDR 0xc0010112 189 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 190 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 191 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 192 193 /* K7 MSRs */ 194 #define MSR_K7_EVNTSEL0 0xc0010000 195 #define MSR_K7_PERFCTR0 0xc0010004 196 #define MSR_K7_EVNTSEL1 0xc0010001 197 #define MSR_K7_PERFCTR1 0xc0010005 198 #define MSR_K7_EVNTSEL2 0xc0010002 199 #define MSR_K7_PERFCTR2 0xc0010006 200 #define MSR_K7_EVNTSEL3 0xc0010003 201 #define MSR_K7_PERFCTR3 0xc0010007 202 #define MSR_K7_CLK_CTL 0xc001001b 203 #define MSR_K7_HWCR 0xc0010015 204 #define MSR_K7_FID_VID_CTL 0xc0010041 205 #define MSR_K7_FID_VID_STATUS 0xc0010042 206 207 /* K6 MSRs */ 208 #define MSR_K6_EFER 0xc0000080 209 #define MSR_K6_STAR 0xc0000081 210 #define MSR_K6_WHCR 0xc0000082 211 #define MSR_K6_UWCCR 0xc0000085 212 #define MSR_K6_EPMR 0xc0000086 213 #define MSR_K6_PSOR 0xc0000087 214 #define MSR_K6_PFIR 0xc0000088 215 216 /* Centaur-Hauls/IDT defined MSRs. */ 217 #define MSR_IDT_FCR1 0x00000107 218 #define MSR_IDT_FCR2 0x00000108 219 #define MSR_IDT_FCR3 0x00000109 220 #define MSR_IDT_FCR4 0x0000010a 221 222 #define MSR_IDT_MCR0 0x00000110 223 #define MSR_IDT_MCR1 0x00000111 224 #define MSR_IDT_MCR2 0x00000112 225 #define MSR_IDT_MCR3 0x00000113 226 #define MSR_IDT_MCR4 0x00000114 227 #define MSR_IDT_MCR5 0x00000115 228 #define MSR_IDT_MCR6 0x00000116 229 #define MSR_IDT_MCR7 0x00000117 230 #define MSR_IDT_MCR_CTRL 0x00000120 231 232 /* VIA Cyrix defined MSRs*/ 233 #define MSR_VIA_FCR 0x00001107 234 #define MSR_VIA_LONGHAUL 0x0000110a 235 #define MSR_VIA_RNG 0x0000110b 236 #define MSR_VIA_BCR2 0x00001147 237 238 /* Transmeta defined MSRs */ 239 #define MSR_TMTA_LONGRUN_CTRL 0x80868010 240 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 241 #define MSR_TMTA_LRTI_READOUT 0x80868018 242 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 243 244 /* Intel defined MSRs. */ 245 #define MSR_IA32_P5_MC_ADDR 0x00000000 246 #define MSR_IA32_P5_MC_TYPE 0x00000001 247 #define MSR_IA32_TSC 0x00000010 248 #define MSR_IA32_PLATFORM_ID 0x00000017 249 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 250 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 251 #define MSR_IA32_TSC_ADJUST 0x0000003b 252 #define MSR_IA32_U_CET 0x000006a0 253 #define MSR_IA32_PL3_SSP 0x000006a7 254 #define MSR_IA32_PKRS 0x000006e1 255 256 #define FEATURE_CONTROL_LOCKED (1<<0) 257 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 258 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 259 260 #define MSR_IA32_APICBASE 0x0000001b 261 #define MSR_IA32_APICBASE_BSP (1<<8) 262 #define MSR_IA32_APICBASE_ENABLE (1<<11) 263 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 264 265 #define MSR_IA32_UCODE_WRITE 0x00000079 266 #define MSR_IA32_UCODE_REV 0x0000008b 267 268 #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 269 #define ARCH_CAP_RDCL_NO (1ULL << 0) 270 #define ARCH_CAP_IBRS_ALL (1ULL << 1) 271 #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH (1ULL << 3) 272 #define ARCH_CAP_SSB_NO (1ULL << 4) 273 #define ARCH_CAP_MDS_NO (1ULL << 5) 274 #define ARCH_CAP_PSCHANGE_MC_NO (1ULL << 6) 275 #define ARCH_CAP_TSX_CTRL_MSR (1ULL << 7) 276 #define ARCH_CAP_TAA_NO (1ULL << 8) 277 278 #define MSR_IA32_TSX_CTRL 0x00000122 279 #define TSX_CTRL_RTM_DISABLE (1ULL << 0) 280 #define TSX_CTRL_CPUID_CLEAR (1ULL << 1) 281 282 #define MSR_IA32_PERF_STATUS 0x00000198 283 #define MSR_IA32_PERF_CTL 0x00000199 284 285 #define MSR_IA32_MPERF 0x000000e7 286 #define MSR_IA32_APERF 0x000000e8 287 288 #define MSR_IA32_THERM_CONTROL 0x0000019a 289 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 290 291 #define THERM_INT_LOW_ENABLE (1 << 0) 292 #define THERM_INT_HIGH_ENABLE (1 << 1) 293 294 #define MSR_IA32_THERM_STATUS 0x0000019c 295 296 #define THERM_STATUS_PROCHOT (1 << 0) 297 298 #define MSR_THERM2_CTL 0x0000019d 299 300 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 301 302 #define MSR_IA32_MISC_ENABLE 0x000001a0 303 304 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 305 306 /* MISC_ENABLE bits: architectural */ 307 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) 308 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) 309 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7) 310 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) 311 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) 312 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16) 313 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 314 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22) 315 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23) 316 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) 317 318 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 319 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2) 320 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3) 321 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4) 322 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) 323 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8) 324 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9) 325 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10) 326 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10) 327 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13) 328 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19) 329 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20) 330 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24) 331 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37) 332 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) 333 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) 334 335 /* P4/Xeon+ specific */ 336 #define MSR_IA32_MCG_EAX 0x00000180 337 #define MSR_IA32_MCG_EBX 0x00000181 338 #define MSR_IA32_MCG_ECX 0x00000182 339 #define MSR_IA32_MCG_EDX 0x00000183 340 #define MSR_IA32_MCG_ESI 0x00000184 341 #define MSR_IA32_MCG_EDI 0x00000185 342 #define MSR_IA32_MCG_EBP 0x00000186 343 #define MSR_IA32_MCG_ESP 0x00000187 344 #define MSR_IA32_MCG_EFLAGS 0x00000188 345 #define MSR_IA32_MCG_EIP 0x00000189 346 #define MSR_IA32_MCG_RESERVED 0x0000018a 347 348 /* Pentium IV performance counter MSRs */ 349 #define MSR_P4_BPU_PERFCTR0 0x00000300 350 #define MSR_P4_BPU_PERFCTR1 0x00000301 351 #define MSR_P4_BPU_PERFCTR2 0x00000302 352 #define MSR_P4_BPU_PERFCTR3 0x00000303 353 #define MSR_P4_MS_PERFCTR0 0x00000304 354 #define MSR_P4_MS_PERFCTR1 0x00000305 355 #define MSR_P4_MS_PERFCTR2 0x00000306 356 #define MSR_P4_MS_PERFCTR3 0x00000307 357 #define MSR_P4_FLAME_PERFCTR0 0x00000308 358 #define MSR_P4_FLAME_PERFCTR1 0x00000309 359 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 360 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 361 #define MSR_P4_IQ_PERFCTR0 0x0000030c 362 #define MSR_P4_IQ_PERFCTR1 0x0000030d 363 #define MSR_P4_IQ_PERFCTR2 0x0000030e 364 #define MSR_P4_IQ_PERFCTR3 0x0000030f 365 #define MSR_P4_IQ_PERFCTR4 0x00000310 366 #define MSR_P4_IQ_PERFCTR5 0x00000311 367 #define MSR_P4_BPU_CCCR0 0x00000360 368 #define MSR_P4_BPU_CCCR1 0x00000361 369 #define MSR_P4_BPU_CCCR2 0x00000362 370 #define MSR_P4_BPU_CCCR3 0x00000363 371 #define MSR_P4_MS_CCCR0 0x00000364 372 #define MSR_P4_MS_CCCR1 0x00000365 373 #define MSR_P4_MS_CCCR2 0x00000366 374 #define MSR_P4_MS_CCCR3 0x00000367 375 #define MSR_P4_FLAME_CCCR0 0x00000368 376 #define MSR_P4_FLAME_CCCR1 0x00000369 377 #define MSR_P4_FLAME_CCCR2 0x0000036a 378 #define MSR_P4_FLAME_CCCR3 0x0000036b 379 #define MSR_P4_IQ_CCCR0 0x0000036c 380 #define MSR_P4_IQ_CCCR1 0x0000036d 381 #define MSR_P4_IQ_CCCR2 0x0000036e 382 #define MSR_P4_IQ_CCCR3 0x0000036f 383 #define MSR_P4_IQ_CCCR4 0x00000370 384 #define MSR_P4_IQ_CCCR5 0x00000371 385 #define MSR_P4_ALF_ESCR0 0x000003ca 386 #define MSR_P4_ALF_ESCR1 0x000003cb 387 #define MSR_P4_BPU_ESCR0 0x000003b2 388 #define MSR_P4_BPU_ESCR1 0x000003b3 389 #define MSR_P4_BSU_ESCR0 0x000003a0 390 #define MSR_P4_BSU_ESCR1 0x000003a1 391 #define MSR_P4_CRU_ESCR0 0x000003b8 392 #define MSR_P4_CRU_ESCR1 0x000003b9 393 #define MSR_P4_CRU_ESCR2 0x000003cc 394 #define MSR_P4_CRU_ESCR3 0x000003cd 395 #define MSR_P4_CRU_ESCR4 0x000003e0 396 #define MSR_P4_CRU_ESCR5 0x000003e1 397 #define MSR_P4_DAC_ESCR0 0x000003a8 398 #define MSR_P4_DAC_ESCR1 0x000003a9 399 #define MSR_P4_FIRM_ESCR0 0x000003a4 400 #define MSR_P4_FIRM_ESCR1 0x000003a5 401 #define MSR_P4_FLAME_ESCR0 0x000003a6 402 #define MSR_P4_FLAME_ESCR1 0x000003a7 403 #define MSR_P4_FSB_ESCR0 0x000003a2 404 #define MSR_P4_FSB_ESCR1 0x000003a3 405 #define MSR_P4_IQ_ESCR0 0x000003ba 406 #define MSR_P4_IQ_ESCR1 0x000003bb 407 #define MSR_P4_IS_ESCR0 0x000003b4 408 #define MSR_P4_IS_ESCR1 0x000003b5 409 #define MSR_P4_ITLB_ESCR0 0x000003b6 410 #define MSR_P4_ITLB_ESCR1 0x000003b7 411 #define MSR_P4_IX_ESCR0 0x000003c8 412 #define MSR_P4_IX_ESCR1 0x000003c9 413 #define MSR_P4_MOB_ESCR0 0x000003aa 414 #define MSR_P4_MOB_ESCR1 0x000003ab 415 #define MSR_P4_MS_ESCR0 0x000003c0 416 #define MSR_P4_MS_ESCR1 0x000003c1 417 #define MSR_P4_PMH_ESCR0 0x000003ac 418 #define MSR_P4_PMH_ESCR1 0x000003ad 419 #define MSR_P4_RAT_ESCR0 0x000003bc 420 #define MSR_P4_RAT_ESCR1 0x000003bd 421 #define MSR_P4_SAAT_ESCR0 0x000003ae 422 #define MSR_P4_SAAT_ESCR1 0x000003af 423 #define MSR_P4_SSU_ESCR0 0x000003be 424 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 425 426 #define MSR_P4_TBPU_ESCR0 0x000003c2 427 #define MSR_P4_TBPU_ESCR1 0x000003c3 428 #define MSR_P4_TC_ESCR0 0x000003c4 429 #define MSR_P4_TC_ESCR1 0x000003c5 430 #define MSR_P4_U2L_ESCR0 0x000003b0 431 #define MSR_P4_U2L_ESCR1 0x000003b1 432 433 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 434 435 /* Intel Core-based CPU performance counters */ 436 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 437 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 438 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 439 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 440 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 441 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 442 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 443 444 /* AMD Performance Counter Global Status and Control MSRs */ 445 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 446 #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 447 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 448 449 /* Geode defined MSRs */ 450 #define MSR_GEODE_BUSCONT_CONF0 0x00001900 451 452 /* Intel VT MSRs */ 453 #define MSR_IA32_VMX_BASIC 0x00000480 454 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 455 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 456 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 457 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 458 #define MSR_IA32_VMX_MISC 0x00000485 459 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 460 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 461 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 462 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 463 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 464 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 465 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 466 #define MSR_IA32_VMX_TRUE_PIN 0x0000048d 467 #define MSR_IA32_VMX_TRUE_PROC 0x0000048e 468 #define MSR_IA32_VMX_TRUE_EXIT 0x0000048f 469 #define MSR_IA32_VMX_TRUE_ENTRY 0x00000490 470 471 /* MSR_IA32_VMX_MISC bits */ 472 #define MSR_IA32_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8) 473 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 474 475 #define MSR_IA32_TSCDEADLINE 0x000006e0 476 477 /* AMD-V MSRs */ 478 479 #define MSR_AMD64_TSC_RATIO 0xc0000104 480 #define MSR_VM_CR 0xc0010114 481 #define MSR_VM_IGNNE 0xc0010115 482 #define MSR_VM_HSAVE_PA 0xc0010117 483 484 #endif /* _X86_MSR_H_ */ 485