1 #include "svm.h" 2 #include "libcflat.h" 3 #include "processor.h" 4 #include "desc.h" 5 #include "msr.h" 6 #include "vm.h" 7 #include "smp.h" 8 #include "types.h" 9 #include "alloc_page.h" 10 #include "isr.h" 11 #include "apic.h" 12 #include "delay.h" 13 14 #define SVM_EXIT_MAX_DR_INTERCEPT 0x3f 15 16 static void *scratch_page; 17 18 #define LATENCY_RUNS 1000000 19 20 extern u16 cpu_online_count; 21 22 u64 tsc_start; 23 u64 tsc_end; 24 25 u64 vmrun_sum, vmexit_sum; 26 u64 vmsave_sum, vmload_sum; 27 u64 stgi_sum, clgi_sum; 28 u64 latvmrun_max; 29 u64 latvmrun_min; 30 u64 latvmexit_max; 31 u64 latvmexit_min; 32 u64 latvmload_max; 33 u64 latvmload_min; 34 u64 latvmsave_max; 35 u64 latvmsave_min; 36 u64 latstgi_max; 37 u64 latstgi_min; 38 u64 latclgi_max; 39 u64 latclgi_min; 40 u64 runs; 41 42 static void null_test(struct svm_test *test) 43 { 44 } 45 46 static bool null_check(struct svm_test *test) 47 { 48 return vmcb->control.exit_code == SVM_EXIT_VMMCALL; 49 } 50 51 static void prepare_no_vmrun_int(struct svm_test *test) 52 { 53 vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMRUN); 54 } 55 56 static bool check_no_vmrun_int(struct svm_test *test) 57 { 58 return vmcb->control.exit_code == SVM_EXIT_ERR; 59 } 60 61 static void test_vmrun(struct svm_test *test) 62 { 63 asm volatile ("vmrun %0" : : "a"(virt_to_phys(vmcb))); 64 } 65 66 static bool check_vmrun(struct svm_test *test) 67 { 68 return vmcb->control.exit_code == SVM_EXIT_VMRUN; 69 } 70 71 static void prepare_rsm_intercept(struct svm_test *test) 72 { 73 default_prepare(test); 74 vmcb->control.intercept |= 1 << INTERCEPT_RSM; 75 vmcb->control.intercept_exceptions |= (1ULL << UD_VECTOR); 76 } 77 78 static void test_rsm_intercept(struct svm_test *test) 79 { 80 asm volatile ("rsm" : : : "memory"); 81 } 82 83 static bool check_rsm_intercept(struct svm_test *test) 84 { 85 return get_test_stage(test) == 2; 86 } 87 88 static bool finished_rsm_intercept(struct svm_test *test) 89 { 90 switch (get_test_stage(test)) { 91 case 0: 92 if (vmcb->control.exit_code != SVM_EXIT_RSM) { 93 report_fail("VMEXIT not due to rsm. Exit reason 0x%x", 94 vmcb->control.exit_code); 95 return true; 96 } 97 vmcb->control.intercept &= ~(1 << INTERCEPT_RSM); 98 inc_test_stage(test); 99 break; 100 101 case 1: 102 if (vmcb->control.exit_code != SVM_EXIT_EXCP_BASE + UD_VECTOR) { 103 report_fail("VMEXIT not due to #UD. Exit reason 0x%x", 104 vmcb->control.exit_code); 105 return true; 106 } 107 vmcb->save.rip += 2; 108 inc_test_stage(test); 109 break; 110 111 default: 112 return true; 113 } 114 return get_test_stage(test) == 2; 115 } 116 117 static void prepare_cr3_intercept(struct svm_test *test) 118 { 119 default_prepare(test); 120 vmcb->control.intercept_cr_read |= 1 << 3; 121 } 122 123 static void test_cr3_intercept(struct svm_test *test) 124 { 125 asm volatile ("mov %%cr3, %0" : "=r"(test->scratch) : : "memory"); 126 } 127 128 static bool check_cr3_intercept(struct svm_test *test) 129 { 130 return vmcb->control.exit_code == SVM_EXIT_READ_CR3; 131 } 132 133 static bool check_cr3_nointercept(struct svm_test *test) 134 { 135 return null_check(test) && test->scratch == read_cr3(); 136 } 137 138 static void corrupt_cr3_intercept_bypass(void *_test) 139 { 140 struct svm_test *test = _test; 141 extern volatile u32 mmio_insn; 142 143 while (!__sync_bool_compare_and_swap(&test->scratch, 1, 2)) 144 pause(); 145 pause(); 146 pause(); 147 pause(); 148 mmio_insn = 0x90d8200f; // mov %cr3, %rax; nop 149 } 150 151 static void prepare_cr3_intercept_bypass(struct svm_test *test) 152 { 153 default_prepare(test); 154 vmcb->control.intercept_cr_read |= 1 << 3; 155 on_cpu_async(1, corrupt_cr3_intercept_bypass, test); 156 } 157 158 static void test_cr3_intercept_bypass(struct svm_test *test) 159 { 160 ulong a = 0xa0000; 161 162 test->scratch = 1; 163 while (test->scratch != 2) 164 barrier(); 165 166 asm volatile ("mmio_insn: mov %0, (%0); nop" 167 : "+a"(a) : : "memory"); 168 test->scratch = a; 169 } 170 171 static void prepare_dr_intercept(struct svm_test *test) 172 { 173 default_prepare(test); 174 vmcb->control.intercept_dr_read = 0xff; 175 vmcb->control.intercept_dr_write = 0xff; 176 } 177 178 static void test_dr_intercept(struct svm_test *test) 179 { 180 unsigned int i, failcnt = 0; 181 182 /* Loop testing debug register reads */ 183 for (i = 0; i < 8; i++) { 184 185 switch (i) { 186 case 0: 187 asm volatile ("mov %%dr0, %0" : "=r"(test->scratch) : : "memory"); 188 break; 189 case 1: 190 asm volatile ("mov %%dr1, %0" : "=r"(test->scratch) : : "memory"); 191 break; 192 case 2: 193 asm volatile ("mov %%dr2, %0" : "=r"(test->scratch) : : "memory"); 194 break; 195 case 3: 196 asm volatile ("mov %%dr3, %0" : "=r"(test->scratch) : : "memory"); 197 break; 198 case 4: 199 asm volatile ("mov %%dr4, %0" : "=r"(test->scratch) : : "memory"); 200 break; 201 case 5: 202 asm volatile ("mov %%dr5, %0" : "=r"(test->scratch) : : "memory"); 203 break; 204 case 6: 205 asm volatile ("mov %%dr6, %0" : "=r"(test->scratch) : : "memory"); 206 break; 207 case 7: 208 asm volatile ("mov %%dr7, %0" : "=r"(test->scratch) : : "memory"); 209 break; 210 } 211 212 if (test->scratch != i) { 213 report_fail("dr%u read intercept", i); 214 failcnt++; 215 } 216 } 217 218 /* Loop testing debug register writes */ 219 for (i = 0; i < 8; i++) { 220 221 switch (i) { 222 case 0: 223 asm volatile ("mov %0, %%dr0" : : "r"(test->scratch) : "memory"); 224 break; 225 case 1: 226 asm volatile ("mov %0, %%dr1" : : "r"(test->scratch) : "memory"); 227 break; 228 case 2: 229 asm volatile ("mov %0, %%dr2" : : "r"(test->scratch) : "memory"); 230 break; 231 case 3: 232 asm volatile ("mov %0, %%dr3" : : "r"(test->scratch) : "memory"); 233 break; 234 case 4: 235 asm volatile ("mov %0, %%dr4" : : "r"(test->scratch) : "memory"); 236 break; 237 case 5: 238 asm volatile ("mov %0, %%dr5" : : "r"(test->scratch) : "memory"); 239 break; 240 case 6: 241 asm volatile ("mov %0, %%dr6" : : "r"(test->scratch) : "memory"); 242 break; 243 case 7: 244 asm volatile ("mov %0, %%dr7" : : "r"(test->scratch) : "memory"); 245 break; 246 } 247 248 if (test->scratch != i) { 249 report_fail("dr%u write intercept", i); 250 failcnt++; 251 } 252 } 253 254 test->scratch = failcnt; 255 } 256 257 static bool dr_intercept_finished(struct svm_test *test) 258 { 259 ulong n = (vmcb->control.exit_code - SVM_EXIT_READ_DR0); 260 261 /* Only expect DR intercepts */ 262 if (n > (SVM_EXIT_MAX_DR_INTERCEPT - SVM_EXIT_READ_DR0)) 263 return true; 264 265 /* 266 * Compute debug register number. 267 * Per Appendix C "SVM Intercept Exit Codes" of AMD64 Architecture 268 * Programmer's Manual Volume 2 - System Programming: 269 * http://support.amd.com/TechDocs/24593.pdf 270 * there are 16 VMEXIT codes each for DR read and write. 271 */ 272 test->scratch = (n % 16); 273 274 /* Jump over MOV instruction */ 275 vmcb->save.rip += 3; 276 277 return false; 278 } 279 280 static bool check_dr_intercept(struct svm_test *test) 281 { 282 return !test->scratch; 283 } 284 285 static bool next_rip_supported(void) 286 { 287 return this_cpu_has(X86_FEATURE_NRIPS); 288 } 289 290 static void prepare_next_rip(struct svm_test *test) 291 { 292 vmcb->control.intercept |= (1ULL << INTERCEPT_RDTSC); 293 } 294 295 296 static void test_next_rip(struct svm_test *test) 297 { 298 asm volatile ("rdtsc\n\t" 299 ".globl exp_next_rip\n\t" 300 "exp_next_rip:\n\t" ::: "eax", "edx"); 301 } 302 303 static bool check_next_rip(struct svm_test *test) 304 { 305 extern char exp_next_rip; 306 unsigned long address = (unsigned long)&exp_next_rip; 307 308 return address == vmcb->control.next_rip; 309 } 310 311 extern u8 *msr_bitmap; 312 313 static void prepare_msr_intercept(struct svm_test *test) 314 { 315 default_prepare(test); 316 vmcb->control.intercept |= (1ULL << INTERCEPT_MSR_PROT); 317 vmcb->control.intercept_exceptions |= (1ULL << GP_VECTOR); 318 memset(msr_bitmap, 0xff, MSR_BITMAP_SIZE); 319 } 320 321 static void test_msr_intercept(struct svm_test *test) 322 { 323 unsigned long msr_value = 0xef8056791234abcd; /* Arbitrary value */ 324 unsigned long msr_index; 325 326 for (msr_index = 0; msr_index <= 0xc0011fff; msr_index++) { 327 if (msr_index == 0xC0010131 /* MSR_SEV_STATUS */) { 328 /* 329 * Per section 15.34.10 "SEV_STATUS MSR" of AMD64 Architecture 330 * Programmer's Manual volume 2 - System Programming: 331 * http://support.amd.com/TechDocs/24593.pdf 332 * SEV_STATUS MSR (C001_0131) is a non-interceptable MSR. 333 */ 334 continue; 335 } 336 337 /* Skips gaps between supported MSR ranges */ 338 if (msr_index == 0x2000) 339 msr_index = 0xc0000000; 340 else if (msr_index == 0xc0002000) 341 msr_index = 0xc0010000; 342 343 test->scratch = -1; 344 345 rdmsr(msr_index); 346 347 /* Check that a read intercept occurred for MSR at msr_index */ 348 if (test->scratch != msr_index) 349 report_fail("MSR 0x%lx read intercept", msr_index); 350 351 /* 352 * Poor man approach to generate a value that 353 * seems arbitrary each time around the loop. 354 */ 355 msr_value += (msr_value << 1); 356 357 wrmsr(msr_index, msr_value); 358 359 /* Check that a write intercept occurred for MSR with msr_value */ 360 if (test->scratch != msr_value) 361 report_fail("MSR 0x%lx write intercept", msr_index); 362 } 363 364 test->scratch = -2; 365 } 366 367 static bool msr_intercept_finished(struct svm_test *test) 368 { 369 u32 exit_code = vmcb->control.exit_code; 370 u64 exit_info_1; 371 u8 *opcode; 372 373 if (exit_code == SVM_EXIT_MSR) { 374 exit_info_1 = vmcb->control.exit_info_1; 375 } else { 376 /* 377 * If #GP exception occurs instead, check that it was 378 * for RDMSR/WRMSR and set exit_info_1 accordingly. 379 */ 380 381 if (exit_code != (SVM_EXIT_EXCP_BASE + GP_VECTOR)) 382 return true; 383 384 opcode = (u8 *)vmcb->save.rip; 385 if (opcode[0] != 0x0f) 386 return true; 387 388 switch (opcode[1]) { 389 case 0x30: /* WRMSR */ 390 exit_info_1 = 1; 391 break; 392 case 0x32: /* RDMSR */ 393 exit_info_1 = 0; 394 break; 395 default: 396 return true; 397 } 398 399 /* 400 * Warn that #GP exception occured instead. 401 * RCX holds the MSR index. 402 */ 403 printf("%s 0x%lx #GP exception\n", 404 exit_info_1 ? "WRMSR" : "RDMSR", get_regs().rcx); 405 } 406 407 /* Jump over RDMSR/WRMSR instruction */ 408 vmcb->save.rip += 2; 409 410 /* 411 * Test whether the intercept was for RDMSR/WRMSR. 412 * For RDMSR, test->scratch is set to the MSR index; 413 * RCX holds the MSR index. 414 * For WRMSR, test->scratch is set to the MSR value; 415 * RDX holds the upper 32 bits of the MSR value, 416 * while RAX hold its lower 32 bits. 417 */ 418 if (exit_info_1) 419 test->scratch = 420 ((get_regs().rdx << 32) | (vmcb->save.rax & 0xffffffff)); 421 else 422 test->scratch = get_regs().rcx; 423 424 return false; 425 } 426 427 static bool check_msr_intercept(struct svm_test *test) 428 { 429 memset(msr_bitmap, 0, MSR_BITMAP_SIZE); 430 return (test->scratch == -2); 431 } 432 433 static void prepare_mode_switch(struct svm_test *test) 434 { 435 vmcb->control.intercept_exceptions |= (1ULL << GP_VECTOR) 436 | (1ULL << UD_VECTOR) 437 | (1ULL << DF_VECTOR) 438 | (1ULL << PF_VECTOR); 439 test->scratch = 0; 440 } 441 442 static void test_mode_switch(struct svm_test *test) 443 { 444 asm volatile(" cli\n" 445 " ljmp *1f\n" /* jump to 32-bit code segment */ 446 "1:\n" 447 " .long 2f\n" 448 " .long " xstr(KERNEL_CS32) "\n" 449 ".code32\n" 450 "2:\n" 451 " movl %%cr0, %%eax\n" 452 " btcl $31, %%eax\n" /* clear PG */ 453 " movl %%eax, %%cr0\n" 454 " movl $0xc0000080, %%ecx\n" /* EFER */ 455 " rdmsr\n" 456 " btcl $8, %%eax\n" /* clear LME */ 457 " wrmsr\n" 458 " movl %%cr4, %%eax\n" 459 " btcl $5, %%eax\n" /* clear PAE */ 460 " movl %%eax, %%cr4\n" 461 " movw %[ds16], %%ax\n" 462 " movw %%ax, %%ds\n" 463 " ljmpl %[cs16], $3f\n" /* jump to 16 bit protected-mode */ 464 ".code16\n" 465 "3:\n" 466 " movl %%cr0, %%eax\n" 467 " btcl $0, %%eax\n" /* clear PE */ 468 " movl %%eax, %%cr0\n" 469 " ljmpl $0, $4f\n" /* jump to real-mode */ 470 "4:\n" 471 " vmmcall\n" 472 " movl %%cr0, %%eax\n" 473 " btsl $0, %%eax\n" /* set PE */ 474 " movl %%eax, %%cr0\n" 475 " ljmpl %[cs32], $5f\n" /* back to protected mode */ 476 ".code32\n" 477 "5:\n" 478 " movl %%cr4, %%eax\n" 479 " btsl $5, %%eax\n" /* set PAE */ 480 " movl %%eax, %%cr4\n" 481 " movl $0xc0000080, %%ecx\n" /* EFER */ 482 " rdmsr\n" 483 " btsl $8, %%eax\n" /* set LME */ 484 " wrmsr\n" 485 " movl %%cr0, %%eax\n" 486 " btsl $31, %%eax\n" /* set PG */ 487 " movl %%eax, %%cr0\n" 488 " ljmpl %[cs64], $6f\n" /* back to long mode */ 489 ".code64\n\t" 490 "6:\n" 491 " vmmcall\n" 492 :: [cs16] "i"(KERNEL_CS16), [ds16] "i"(KERNEL_DS16), 493 [cs32] "i"(KERNEL_CS32), [cs64] "i"(KERNEL_CS64) 494 : "rax", "rbx", "rcx", "rdx", "memory"); 495 } 496 497 static bool mode_switch_finished(struct svm_test *test) 498 { 499 u64 cr0, cr4, efer; 500 501 cr0 = vmcb->save.cr0; 502 cr4 = vmcb->save.cr4; 503 efer = vmcb->save.efer; 504 505 /* Only expect VMMCALL intercepts */ 506 if (vmcb->control.exit_code != SVM_EXIT_VMMCALL) 507 return true; 508 509 /* Jump over VMMCALL instruction */ 510 vmcb->save.rip += 3; 511 512 /* Do sanity checks */ 513 switch (test->scratch) { 514 case 0: 515 /* Test should be in real mode now - check for this */ 516 if ((cr0 & 0x80000001) || /* CR0.PG, CR0.PE */ 517 (cr4 & 0x00000020) || /* CR4.PAE */ 518 (efer & 0x00000500)) /* EFER.LMA, EFER.LME */ 519 return true; 520 break; 521 case 2: 522 /* Test should be back in long-mode now - check for this */ 523 if (((cr0 & 0x80000001) != 0x80000001) || /* CR0.PG, CR0.PE */ 524 ((cr4 & 0x00000020) != 0x00000020) || /* CR4.PAE */ 525 ((efer & 0x00000500) != 0x00000500)) /* EFER.LMA, EFER.LME */ 526 return true; 527 break; 528 } 529 530 /* one step forward */ 531 test->scratch += 1; 532 533 return test->scratch == 2; 534 } 535 536 static bool check_mode_switch(struct svm_test *test) 537 { 538 return test->scratch == 2; 539 } 540 541 extern u8 *io_bitmap; 542 543 static void prepare_ioio(struct svm_test *test) 544 { 545 vmcb->control.intercept |= (1ULL << INTERCEPT_IOIO_PROT); 546 test->scratch = 0; 547 memset(io_bitmap, 0, 8192); 548 io_bitmap[8192] = 0xFF; 549 } 550 551 static void test_ioio(struct svm_test *test) 552 { 553 // stage 0, test IO pass 554 inb(0x5000); 555 outb(0x0, 0x5000); 556 if (get_test_stage(test) != 0) 557 goto fail; 558 559 // test IO width, in/out 560 io_bitmap[0] = 0xFF; 561 inc_test_stage(test); 562 inb(0x0); 563 if (get_test_stage(test) != 2) 564 goto fail; 565 566 outw(0x0, 0x0); 567 if (get_test_stage(test) != 3) 568 goto fail; 569 570 inl(0x0); 571 if (get_test_stage(test) != 4) 572 goto fail; 573 574 // test low/high IO port 575 io_bitmap[0x5000 / 8] = (1 << (0x5000 % 8)); 576 inb(0x5000); 577 if (get_test_stage(test) != 5) 578 goto fail; 579 580 io_bitmap[0x9000 / 8] = (1 << (0x9000 % 8)); 581 inw(0x9000); 582 if (get_test_stage(test) != 6) 583 goto fail; 584 585 // test partial pass 586 io_bitmap[0x5000 / 8] = (1 << (0x5000 % 8)); 587 inl(0x4FFF); 588 if (get_test_stage(test) != 7) 589 goto fail; 590 591 // test across pages 592 inc_test_stage(test); 593 inl(0x7FFF); 594 if (get_test_stage(test) != 8) 595 goto fail; 596 597 inc_test_stage(test); 598 io_bitmap[0x8000 / 8] = 1 << (0x8000 % 8); 599 inl(0x7FFF); 600 if (get_test_stage(test) != 10) 601 goto fail; 602 603 io_bitmap[0] = 0; 604 inl(0xFFFF); 605 if (get_test_stage(test) != 11) 606 goto fail; 607 608 io_bitmap[0] = 0xFF; 609 io_bitmap[8192] = 0; 610 inl(0xFFFF); 611 inc_test_stage(test); 612 if (get_test_stage(test) != 12) 613 goto fail; 614 615 return; 616 617 fail: 618 report_fail("stage %d", get_test_stage(test)); 619 test->scratch = -1; 620 } 621 622 static bool ioio_finished(struct svm_test *test) 623 { 624 unsigned port, size; 625 626 /* Only expect IOIO intercepts */ 627 if (vmcb->control.exit_code == SVM_EXIT_VMMCALL) 628 return true; 629 630 if (vmcb->control.exit_code != SVM_EXIT_IOIO) 631 return true; 632 633 /* one step forward */ 634 test->scratch += 1; 635 636 port = vmcb->control.exit_info_1 >> 16; 637 size = (vmcb->control.exit_info_1 >> SVM_IOIO_SIZE_SHIFT) & 7; 638 639 while (size--) { 640 io_bitmap[port / 8] &= ~(1 << (port & 7)); 641 port++; 642 } 643 644 return false; 645 } 646 647 static bool check_ioio(struct svm_test *test) 648 { 649 memset(io_bitmap, 0, 8193); 650 return test->scratch != -1; 651 } 652 653 static void prepare_asid_zero(struct svm_test *test) 654 { 655 vmcb->control.asid = 0; 656 } 657 658 static void test_asid_zero(struct svm_test *test) 659 { 660 asm volatile ("vmmcall\n\t"); 661 } 662 663 static bool check_asid_zero(struct svm_test *test) 664 { 665 return vmcb->control.exit_code == SVM_EXIT_ERR; 666 } 667 668 static void sel_cr0_bug_prepare(struct svm_test *test) 669 { 670 vmcb->control.intercept |= (1ULL << INTERCEPT_SELECTIVE_CR0); 671 } 672 673 static bool sel_cr0_bug_finished(struct svm_test *test) 674 { 675 return true; 676 } 677 678 static void sel_cr0_bug_test(struct svm_test *test) 679 { 680 unsigned long cr0; 681 682 /* read cr0, clear CD, and write back */ 683 cr0 = read_cr0(); 684 cr0 |= (1UL << 30); 685 write_cr0(cr0); 686 687 /* 688 * If we are here the test failed, not sure what to do now because we 689 * are not in guest-mode anymore so we can't trigger an intercept. 690 * Trigger a tripple-fault for now. 691 */ 692 report_fail("sel_cr0 test. Can not recover from this - exiting"); 693 exit(report_summary()); 694 } 695 696 static bool sel_cr0_bug_check(struct svm_test *test) 697 { 698 return vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE; 699 } 700 701 static void npt_nx_prepare(struct svm_test *test) 702 { 703 u64 *pte; 704 705 test->scratch = rdmsr(MSR_EFER); 706 wrmsr(MSR_EFER, test->scratch | EFER_NX); 707 708 /* Clear the guest's EFER.NX, it should not affect NPT behavior. */ 709 vmcb->save.efer &= ~EFER_NX; 710 711 pte = npt_get_pte((u64)null_test); 712 713 *pte |= PT64_NX_MASK; 714 } 715 716 static bool npt_nx_check(struct svm_test *test) 717 { 718 u64 *pte = npt_get_pte((u64)null_test); 719 720 wrmsr(MSR_EFER, test->scratch); 721 722 *pte &= ~PT64_NX_MASK; 723 724 return (vmcb->control.exit_code == SVM_EXIT_NPF) 725 && (vmcb->control.exit_info_1 == 0x100000015ULL); 726 } 727 728 static void npt_np_prepare(struct svm_test *test) 729 { 730 u64 *pte; 731 732 scratch_page = alloc_page(); 733 pte = npt_get_pte((u64)scratch_page); 734 735 *pte &= ~1ULL; 736 } 737 738 static void npt_np_test(struct svm_test *test) 739 { 740 (void) *(volatile u64 *)scratch_page; 741 } 742 743 static bool npt_np_check(struct svm_test *test) 744 { 745 u64 *pte = npt_get_pte((u64)scratch_page); 746 747 *pte |= 1ULL; 748 749 return (vmcb->control.exit_code == SVM_EXIT_NPF) 750 && (vmcb->control.exit_info_1 == 0x100000004ULL); 751 } 752 753 static void npt_us_prepare(struct svm_test *test) 754 { 755 u64 *pte; 756 757 scratch_page = alloc_page(); 758 pte = npt_get_pte((u64)scratch_page); 759 760 *pte &= ~(1ULL << 2); 761 } 762 763 static void npt_us_test(struct svm_test *test) 764 { 765 (void) *(volatile u64 *)scratch_page; 766 } 767 768 static bool npt_us_check(struct svm_test *test) 769 { 770 u64 *pte = npt_get_pte((u64)scratch_page); 771 772 *pte |= (1ULL << 2); 773 774 return (vmcb->control.exit_code == SVM_EXIT_NPF) 775 && (vmcb->control.exit_info_1 == 0x100000005ULL); 776 } 777 778 static void npt_rw_prepare(struct svm_test *test) 779 { 780 781 u64 *pte; 782 783 pte = npt_get_pte(0x80000); 784 785 *pte &= ~(1ULL << 1); 786 } 787 788 static void npt_rw_test(struct svm_test *test) 789 { 790 u64 *data = (void*)(0x80000); 791 792 *data = 0; 793 } 794 795 static bool npt_rw_check(struct svm_test *test) 796 { 797 u64 *pte = npt_get_pte(0x80000); 798 799 *pte |= (1ULL << 1); 800 801 return (vmcb->control.exit_code == SVM_EXIT_NPF) 802 && (vmcb->control.exit_info_1 == 0x100000007ULL); 803 } 804 805 static void npt_rw_pfwalk_prepare(struct svm_test *test) 806 { 807 808 u64 *pte; 809 810 pte = npt_get_pte(read_cr3()); 811 812 *pte &= ~(1ULL << 1); 813 } 814 815 static bool npt_rw_pfwalk_check(struct svm_test *test) 816 { 817 u64 *pte = npt_get_pte(read_cr3()); 818 819 *pte |= (1ULL << 1); 820 821 return (vmcb->control.exit_code == SVM_EXIT_NPF) 822 && (vmcb->control.exit_info_1 == 0x200000007ULL) 823 && (vmcb->control.exit_info_2 == read_cr3()); 824 } 825 826 static void npt_l1mmio_prepare(struct svm_test *test) 827 { 828 } 829 830 u32 nested_apic_version1; 831 u32 nested_apic_version2; 832 833 static void npt_l1mmio_test(struct svm_test *test) 834 { 835 volatile u32 *data = (volatile void*)(0xfee00030UL); 836 837 nested_apic_version1 = *data; 838 nested_apic_version2 = *data; 839 } 840 841 static bool npt_l1mmio_check(struct svm_test *test) 842 { 843 volatile u32 *data = (volatile void*)(0xfee00030); 844 u32 lvr = *data; 845 846 return nested_apic_version1 == lvr && nested_apic_version2 == lvr; 847 } 848 849 static void npt_rw_l1mmio_prepare(struct svm_test *test) 850 { 851 852 u64 *pte; 853 854 pte = npt_get_pte(0xfee00080); 855 856 *pte &= ~(1ULL << 1); 857 } 858 859 static void npt_rw_l1mmio_test(struct svm_test *test) 860 { 861 volatile u32 *data = (volatile void*)(0xfee00080); 862 863 *data = *data; 864 } 865 866 static bool npt_rw_l1mmio_check(struct svm_test *test) 867 { 868 u64 *pte = npt_get_pte(0xfee00080); 869 870 *pte |= (1ULL << 1); 871 872 return (vmcb->control.exit_code == SVM_EXIT_NPF) 873 && (vmcb->control.exit_info_1 == 0x100000007ULL); 874 } 875 876 #define TSC_ADJUST_VALUE (1ll << 32) 877 #define TSC_OFFSET_VALUE (~0ull << 48) 878 static bool ok; 879 880 static bool tsc_adjust_supported(void) 881 { 882 return this_cpu_has(X86_FEATURE_TSC_ADJUST); 883 } 884 885 static void tsc_adjust_prepare(struct svm_test *test) 886 { 887 default_prepare(test); 888 vmcb->control.tsc_offset = TSC_OFFSET_VALUE; 889 890 wrmsr(MSR_IA32_TSC_ADJUST, -TSC_ADJUST_VALUE); 891 int64_t adjust = rdmsr(MSR_IA32_TSC_ADJUST); 892 ok = adjust == -TSC_ADJUST_VALUE; 893 } 894 895 static void tsc_adjust_test(struct svm_test *test) 896 { 897 int64_t adjust = rdmsr(MSR_IA32_TSC_ADJUST); 898 ok &= adjust == -TSC_ADJUST_VALUE; 899 900 uint64_t l1_tsc = rdtsc() - TSC_OFFSET_VALUE; 901 wrmsr(MSR_IA32_TSC, l1_tsc - TSC_ADJUST_VALUE); 902 903 adjust = rdmsr(MSR_IA32_TSC_ADJUST); 904 ok &= adjust <= -2 * TSC_ADJUST_VALUE; 905 906 uint64_t l1_tsc_end = rdtsc() - TSC_OFFSET_VALUE; 907 ok &= (l1_tsc_end + TSC_ADJUST_VALUE - l1_tsc) < TSC_ADJUST_VALUE; 908 909 uint64_t l1_tsc_msr = rdmsr(MSR_IA32_TSC) - TSC_OFFSET_VALUE; 910 ok &= (l1_tsc_msr + TSC_ADJUST_VALUE - l1_tsc) < TSC_ADJUST_VALUE; 911 } 912 913 static bool tsc_adjust_check(struct svm_test *test) 914 { 915 int64_t adjust = rdmsr(MSR_IA32_TSC_ADJUST); 916 917 wrmsr(MSR_IA32_TSC_ADJUST, 0); 918 return ok && adjust <= -2 * TSC_ADJUST_VALUE; 919 } 920 921 static void latency_prepare(struct svm_test *test) 922 { 923 default_prepare(test); 924 runs = LATENCY_RUNS; 925 latvmrun_min = latvmexit_min = -1ULL; 926 latvmrun_max = latvmexit_max = 0; 927 vmrun_sum = vmexit_sum = 0; 928 tsc_start = rdtsc(); 929 } 930 931 static void latency_test(struct svm_test *test) 932 { 933 u64 cycles; 934 935 start: 936 tsc_end = rdtsc(); 937 938 cycles = tsc_end - tsc_start; 939 940 if (cycles > latvmrun_max) 941 latvmrun_max = cycles; 942 943 if (cycles < latvmrun_min) 944 latvmrun_min = cycles; 945 946 vmrun_sum += cycles; 947 948 tsc_start = rdtsc(); 949 950 asm volatile ("vmmcall" : : : "memory"); 951 goto start; 952 } 953 954 static bool latency_finished(struct svm_test *test) 955 { 956 u64 cycles; 957 958 tsc_end = rdtsc(); 959 960 cycles = tsc_end - tsc_start; 961 962 if (cycles > latvmexit_max) 963 latvmexit_max = cycles; 964 965 if (cycles < latvmexit_min) 966 latvmexit_min = cycles; 967 968 vmexit_sum += cycles; 969 970 vmcb->save.rip += 3; 971 972 runs -= 1; 973 974 tsc_end = rdtsc(); 975 976 return runs == 0; 977 } 978 979 static bool latency_finished_clean(struct svm_test *test) 980 { 981 vmcb->control.clean = VMCB_CLEAN_ALL; 982 return latency_finished(test); 983 } 984 985 static bool latency_check(struct svm_test *test) 986 { 987 printf(" Latency VMRUN : max: %ld min: %ld avg: %ld\n", latvmrun_max, 988 latvmrun_min, vmrun_sum / LATENCY_RUNS); 989 printf(" Latency VMEXIT: max: %ld min: %ld avg: %ld\n", latvmexit_max, 990 latvmexit_min, vmexit_sum / LATENCY_RUNS); 991 return true; 992 } 993 994 static void lat_svm_insn_prepare(struct svm_test *test) 995 { 996 default_prepare(test); 997 runs = LATENCY_RUNS; 998 latvmload_min = latvmsave_min = latstgi_min = latclgi_min = -1ULL; 999 latvmload_max = latvmsave_max = latstgi_max = latclgi_max = 0; 1000 vmload_sum = vmsave_sum = stgi_sum = clgi_sum; 1001 } 1002 1003 static bool lat_svm_insn_finished(struct svm_test *test) 1004 { 1005 u64 vmcb_phys = virt_to_phys(vmcb); 1006 u64 cycles; 1007 1008 for ( ; runs != 0; runs--) { 1009 tsc_start = rdtsc(); 1010 asm volatile("vmload %0\n\t" : : "a"(vmcb_phys) : "memory"); 1011 cycles = rdtsc() - tsc_start; 1012 if (cycles > latvmload_max) 1013 latvmload_max = cycles; 1014 if (cycles < latvmload_min) 1015 latvmload_min = cycles; 1016 vmload_sum += cycles; 1017 1018 tsc_start = rdtsc(); 1019 asm volatile("vmsave %0\n\t" : : "a"(vmcb_phys) : "memory"); 1020 cycles = rdtsc() - tsc_start; 1021 if (cycles > latvmsave_max) 1022 latvmsave_max = cycles; 1023 if (cycles < latvmsave_min) 1024 latvmsave_min = cycles; 1025 vmsave_sum += cycles; 1026 1027 tsc_start = rdtsc(); 1028 asm volatile("stgi\n\t"); 1029 cycles = rdtsc() - tsc_start; 1030 if (cycles > latstgi_max) 1031 latstgi_max = cycles; 1032 if (cycles < latstgi_min) 1033 latstgi_min = cycles; 1034 stgi_sum += cycles; 1035 1036 tsc_start = rdtsc(); 1037 asm volatile("clgi\n\t"); 1038 cycles = rdtsc() - tsc_start; 1039 if (cycles > latclgi_max) 1040 latclgi_max = cycles; 1041 if (cycles < latclgi_min) 1042 latclgi_min = cycles; 1043 clgi_sum += cycles; 1044 } 1045 1046 tsc_end = rdtsc(); 1047 1048 return true; 1049 } 1050 1051 static bool lat_svm_insn_check(struct svm_test *test) 1052 { 1053 printf(" Latency VMLOAD: max: %ld min: %ld avg: %ld\n", latvmload_max, 1054 latvmload_min, vmload_sum / LATENCY_RUNS); 1055 printf(" Latency VMSAVE: max: %ld min: %ld avg: %ld\n", latvmsave_max, 1056 latvmsave_min, vmsave_sum / LATENCY_RUNS); 1057 printf(" Latency STGI: max: %ld min: %ld avg: %ld\n", latstgi_max, 1058 latstgi_min, stgi_sum / LATENCY_RUNS); 1059 printf(" Latency CLGI: max: %ld min: %ld avg: %ld\n", latclgi_max, 1060 latclgi_min, clgi_sum / LATENCY_RUNS); 1061 return true; 1062 } 1063 1064 bool pending_event_ipi_fired; 1065 bool pending_event_guest_run; 1066 1067 static void pending_event_ipi_isr(isr_regs_t *regs) 1068 { 1069 pending_event_ipi_fired = true; 1070 eoi(); 1071 } 1072 1073 static void pending_event_prepare(struct svm_test *test) 1074 { 1075 int ipi_vector = 0xf1; 1076 1077 default_prepare(test); 1078 1079 pending_event_ipi_fired = false; 1080 1081 handle_irq(ipi_vector, pending_event_ipi_isr); 1082 1083 pending_event_guest_run = false; 1084 1085 vmcb->control.intercept |= (1ULL << INTERCEPT_INTR); 1086 vmcb->control.int_ctl |= V_INTR_MASKING_MASK; 1087 1088 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 1089 APIC_DM_FIXED | ipi_vector, 0); 1090 1091 set_test_stage(test, 0); 1092 } 1093 1094 static void pending_event_test(struct svm_test *test) 1095 { 1096 pending_event_guest_run = true; 1097 } 1098 1099 static bool pending_event_finished(struct svm_test *test) 1100 { 1101 switch (get_test_stage(test)) { 1102 case 0: 1103 if (vmcb->control.exit_code != SVM_EXIT_INTR) { 1104 report_fail("VMEXIT not due to pending interrupt. Exit reason 0x%x", 1105 vmcb->control.exit_code); 1106 return true; 1107 } 1108 1109 vmcb->control.intercept &= ~(1ULL << INTERCEPT_INTR); 1110 vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; 1111 1112 if (pending_event_guest_run) { 1113 report_fail("Guest ran before host received IPI\n"); 1114 return true; 1115 } 1116 1117 irq_enable(); 1118 asm volatile ("nop"); 1119 irq_disable(); 1120 1121 if (!pending_event_ipi_fired) { 1122 report_fail("Pending interrupt not dispatched after IRQ enabled\n"); 1123 return true; 1124 } 1125 break; 1126 1127 case 1: 1128 if (!pending_event_guest_run) { 1129 report_fail("Guest did not resume when no interrupt\n"); 1130 return true; 1131 } 1132 break; 1133 } 1134 1135 inc_test_stage(test); 1136 1137 return get_test_stage(test) == 2; 1138 } 1139 1140 static bool pending_event_check(struct svm_test *test) 1141 { 1142 return get_test_stage(test) == 2; 1143 } 1144 1145 static void pending_event_cli_prepare(struct svm_test *test) 1146 { 1147 default_prepare(test); 1148 1149 pending_event_ipi_fired = false; 1150 1151 handle_irq(0xf1, pending_event_ipi_isr); 1152 1153 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 1154 APIC_DM_FIXED | 0xf1, 0); 1155 1156 set_test_stage(test, 0); 1157 } 1158 1159 static void pending_event_cli_prepare_gif_clear(struct svm_test *test) 1160 { 1161 asm("cli"); 1162 } 1163 1164 static void pending_event_cli_test(struct svm_test *test) 1165 { 1166 if (pending_event_ipi_fired == true) { 1167 set_test_stage(test, -1); 1168 report_fail("Interrupt preceeded guest"); 1169 vmmcall(); 1170 } 1171 1172 /* VINTR_MASKING is zero. This should cause the IPI to fire. */ 1173 irq_enable(); 1174 asm volatile ("nop"); 1175 irq_disable(); 1176 1177 if (pending_event_ipi_fired != true) { 1178 set_test_stage(test, -1); 1179 report_fail("Interrupt not triggered by guest"); 1180 } 1181 1182 vmmcall(); 1183 1184 /* 1185 * Now VINTR_MASKING=1, but no interrupt is pending so 1186 * the VINTR interception should be clear in VMCB02. Check 1187 * that L0 did not leave a stale VINTR in the VMCB. 1188 */ 1189 irq_enable(); 1190 asm volatile ("nop"); 1191 irq_disable(); 1192 } 1193 1194 static bool pending_event_cli_finished(struct svm_test *test) 1195 { 1196 if ( vmcb->control.exit_code != SVM_EXIT_VMMCALL) { 1197 report_fail("VM_EXIT return to host is not EXIT_VMMCALL exit reason 0x%x", 1198 vmcb->control.exit_code); 1199 return true; 1200 } 1201 1202 switch (get_test_stage(test)) { 1203 case 0: 1204 vmcb->save.rip += 3; 1205 1206 pending_event_ipi_fired = false; 1207 1208 vmcb->control.int_ctl |= V_INTR_MASKING_MASK; 1209 1210 /* Now entering again with VINTR_MASKING=1. */ 1211 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 1212 APIC_DM_FIXED | 0xf1, 0); 1213 1214 break; 1215 1216 case 1: 1217 if (pending_event_ipi_fired == true) { 1218 report_fail("Interrupt triggered by guest"); 1219 return true; 1220 } 1221 1222 irq_enable(); 1223 asm volatile ("nop"); 1224 irq_disable(); 1225 1226 if (pending_event_ipi_fired != true) { 1227 report_fail("Interrupt not triggered by host"); 1228 return true; 1229 } 1230 1231 break; 1232 1233 default: 1234 return true; 1235 } 1236 1237 inc_test_stage(test); 1238 1239 return get_test_stage(test) == 2; 1240 } 1241 1242 static bool pending_event_cli_check(struct svm_test *test) 1243 { 1244 return get_test_stage(test) == 2; 1245 } 1246 1247 #define TIMER_VECTOR 222 1248 1249 static volatile bool timer_fired; 1250 1251 static void timer_isr(isr_regs_t *regs) 1252 { 1253 timer_fired = true; 1254 apic_write(APIC_EOI, 0); 1255 } 1256 1257 static void interrupt_prepare(struct svm_test *test) 1258 { 1259 default_prepare(test); 1260 handle_irq(TIMER_VECTOR, timer_isr); 1261 timer_fired = false; 1262 set_test_stage(test, 0); 1263 } 1264 1265 static void interrupt_test(struct svm_test *test) 1266 { 1267 long long start, loops; 1268 1269 apic_write(APIC_LVTT, TIMER_VECTOR); 1270 irq_enable(); 1271 apic_write(APIC_TMICT, 1); //Timer Initial Count Register 0x380 one-shot 1272 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1273 asm volatile ("nop"); 1274 1275 report(timer_fired, "direct interrupt while running guest"); 1276 1277 if (!timer_fired) { 1278 set_test_stage(test, -1); 1279 vmmcall(); 1280 } 1281 1282 apic_write(APIC_TMICT, 0); 1283 irq_disable(); 1284 vmmcall(); 1285 1286 timer_fired = false; 1287 apic_write(APIC_TMICT, 1); 1288 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1289 asm volatile ("nop"); 1290 1291 report(timer_fired, "intercepted interrupt while running guest"); 1292 1293 if (!timer_fired) { 1294 set_test_stage(test, -1); 1295 vmmcall(); 1296 } 1297 1298 irq_enable(); 1299 apic_write(APIC_TMICT, 0); 1300 irq_disable(); 1301 1302 timer_fired = false; 1303 start = rdtsc(); 1304 apic_write(APIC_TMICT, 1000000); 1305 asm volatile ("sti; hlt"); 1306 1307 report(rdtsc() - start > 10000 && timer_fired, 1308 "direct interrupt + hlt"); 1309 1310 if (!timer_fired) { 1311 set_test_stage(test, -1); 1312 vmmcall(); 1313 } 1314 1315 apic_write(APIC_TMICT, 0); 1316 irq_disable(); 1317 vmmcall(); 1318 1319 timer_fired = false; 1320 start = rdtsc(); 1321 apic_write(APIC_TMICT, 1000000); 1322 asm volatile ("hlt"); 1323 1324 report(rdtsc() - start > 10000 && timer_fired, 1325 "intercepted interrupt + hlt"); 1326 1327 if (!timer_fired) { 1328 set_test_stage(test, -1); 1329 vmmcall(); 1330 } 1331 1332 apic_write(APIC_TMICT, 0); 1333 irq_disable(); 1334 } 1335 1336 static bool interrupt_finished(struct svm_test *test) 1337 { 1338 switch (get_test_stage(test)) { 1339 case 0: 1340 case 2: 1341 if (vmcb->control.exit_code != SVM_EXIT_VMMCALL) { 1342 report_fail("VMEXIT not due to vmmcall. Exit reason 0x%x", 1343 vmcb->control.exit_code); 1344 return true; 1345 } 1346 vmcb->save.rip += 3; 1347 1348 vmcb->control.intercept |= (1ULL << INTERCEPT_INTR); 1349 vmcb->control.int_ctl |= V_INTR_MASKING_MASK; 1350 break; 1351 1352 case 1: 1353 case 3: 1354 if (vmcb->control.exit_code != SVM_EXIT_INTR) { 1355 report_fail("VMEXIT not due to intr intercept. Exit reason 0x%x", 1356 vmcb->control.exit_code); 1357 return true; 1358 } 1359 1360 irq_enable(); 1361 asm volatile ("nop"); 1362 irq_disable(); 1363 1364 vmcb->control.intercept &= ~(1ULL << INTERCEPT_INTR); 1365 vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; 1366 break; 1367 1368 case 4: 1369 break; 1370 1371 default: 1372 return true; 1373 } 1374 1375 inc_test_stage(test); 1376 1377 return get_test_stage(test) == 5; 1378 } 1379 1380 static bool interrupt_check(struct svm_test *test) 1381 { 1382 return get_test_stage(test) == 5; 1383 } 1384 1385 static volatile bool nmi_fired; 1386 1387 static void nmi_handler(isr_regs_t *regs) 1388 { 1389 nmi_fired = true; 1390 apic_write(APIC_EOI, 0); 1391 } 1392 1393 static void nmi_prepare(struct svm_test *test) 1394 { 1395 default_prepare(test); 1396 nmi_fired = false; 1397 handle_irq(NMI_VECTOR, nmi_handler); 1398 set_test_stage(test, 0); 1399 } 1400 1401 static void nmi_test(struct svm_test *test) 1402 { 1403 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, 0); 1404 1405 report(nmi_fired, "direct NMI while running guest"); 1406 1407 if (!nmi_fired) 1408 set_test_stage(test, -1); 1409 1410 vmmcall(); 1411 1412 nmi_fired = false; 1413 1414 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, 0); 1415 1416 if (!nmi_fired) { 1417 report(nmi_fired, "intercepted pending NMI not dispatched"); 1418 set_test_stage(test, -1); 1419 } 1420 1421 } 1422 1423 static bool nmi_finished(struct svm_test *test) 1424 { 1425 switch (get_test_stage(test)) { 1426 case 0: 1427 if (vmcb->control.exit_code != SVM_EXIT_VMMCALL) { 1428 report_fail("VMEXIT not due to vmmcall. Exit reason 0x%x", 1429 vmcb->control.exit_code); 1430 return true; 1431 } 1432 vmcb->save.rip += 3; 1433 1434 vmcb->control.intercept |= (1ULL << INTERCEPT_NMI); 1435 break; 1436 1437 case 1: 1438 if (vmcb->control.exit_code != SVM_EXIT_NMI) { 1439 report_fail("VMEXIT not due to NMI intercept. Exit reason 0x%x", 1440 vmcb->control.exit_code); 1441 return true; 1442 } 1443 1444 report_pass("NMI intercept while running guest"); 1445 break; 1446 1447 case 2: 1448 break; 1449 1450 default: 1451 return true; 1452 } 1453 1454 inc_test_stage(test); 1455 1456 return get_test_stage(test) == 3; 1457 } 1458 1459 static bool nmi_check(struct svm_test *test) 1460 { 1461 return get_test_stage(test) == 3; 1462 } 1463 1464 #define NMI_DELAY 100000000ULL 1465 1466 static void nmi_message_thread(void *_test) 1467 { 1468 struct svm_test *test = _test; 1469 1470 while (get_test_stage(test) != 1) 1471 pause(); 1472 1473 delay(NMI_DELAY); 1474 1475 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1476 1477 while (get_test_stage(test) != 2) 1478 pause(); 1479 1480 delay(NMI_DELAY); 1481 1482 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1483 } 1484 1485 static void nmi_hlt_test(struct svm_test *test) 1486 { 1487 long long start; 1488 1489 on_cpu_async(1, nmi_message_thread, test); 1490 1491 start = rdtsc(); 1492 1493 set_test_stage(test, 1); 1494 1495 asm volatile ("hlt"); 1496 1497 report((rdtsc() - start > NMI_DELAY) && nmi_fired, 1498 "direct NMI + hlt"); 1499 1500 if (!nmi_fired) 1501 set_test_stage(test, -1); 1502 1503 nmi_fired = false; 1504 1505 vmmcall(); 1506 1507 start = rdtsc(); 1508 1509 set_test_stage(test, 2); 1510 1511 asm volatile ("hlt"); 1512 1513 report((rdtsc() - start > NMI_DELAY) && nmi_fired, 1514 "intercepted NMI + hlt"); 1515 1516 if (!nmi_fired) { 1517 report(nmi_fired, "intercepted pending NMI not dispatched"); 1518 set_test_stage(test, -1); 1519 vmmcall(); 1520 } 1521 1522 set_test_stage(test, 3); 1523 } 1524 1525 static bool nmi_hlt_finished(struct svm_test *test) 1526 { 1527 switch (get_test_stage(test)) { 1528 case 1: 1529 if (vmcb->control.exit_code != SVM_EXIT_VMMCALL) { 1530 report_fail("VMEXIT not due to vmmcall. Exit reason 0x%x", 1531 vmcb->control.exit_code); 1532 return true; 1533 } 1534 vmcb->save.rip += 3; 1535 1536 vmcb->control.intercept |= (1ULL << INTERCEPT_NMI); 1537 break; 1538 1539 case 2: 1540 if (vmcb->control.exit_code != SVM_EXIT_NMI) { 1541 report_fail("VMEXIT not due to NMI intercept. Exit reason 0x%x", 1542 vmcb->control.exit_code); 1543 return true; 1544 } 1545 1546 report_pass("NMI intercept while running guest"); 1547 break; 1548 1549 case 3: 1550 break; 1551 1552 default: 1553 return true; 1554 } 1555 1556 return get_test_stage(test) == 3; 1557 } 1558 1559 static bool nmi_hlt_check(struct svm_test *test) 1560 { 1561 return get_test_stage(test) == 3; 1562 } 1563 1564 static volatile int count_exc = 0; 1565 1566 static void my_isr(struct ex_regs *r) 1567 { 1568 count_exc++; 1569 } 1570 1571 static void exc_inject_prepare(struct svm_test *test) 1572 { 1573 default_prepare(test); 1574 handle_exception(DE_VECTOR, my_isr); 1575 handle_exception(NMI_VECTOR, my_isr); 1576 } 1577 1578 1579 static void exc_inject_test(struct svm_test *test) 1580 { 1581 asm volatile ("vmmcall\n\tvmmcall\n\t"); 1582 } 1583 1584 static bool exc_inject_finished(struct svm_test *test) 1585 { 1586 switch (get_test_stage(test)) { 1587 case 0: 1588 if (vmcb->control.exit_code != SVM_EXIT_VMMCALL) { 1589 report_fail("VMEXIT not due to vmmcall. Exit reason 0x%x", 1590 vmcb->control.exit_code); 1591 return true; 1592 } 1593 vmcb->save.rip += 3; 1594 vmcb->control.event_inj = NMI_VECTOR | SVM_EVTINJ_TYPE_EXEPT | SVM_EVTINJ_VALID; 1595 break; 1596 1597 case 1: 1598 if (vmcb->control.exit_code != SVM_EXIT_ERR) { 1599 report_fail("VMEXIT not due to error. Exit reason 0x%x", 1600 vmcb->control.exit_code); 1601 return true; 1602 } 1603 report(count_exc == 0, "exception with vector 2 not injected"); 1604 vmcb->control.event_inj = DE_VECTOR | SVM_EVTINJ_TYPE_EXEPT | SVM_EVTINJ_VALID; 1605 break; 1606 1607 case 2: 1608 if (vmcb->control.exit_code != SVM_EXIT_VMMCALL) { 1609 report_fail("VMEXIT not due to vmmcall. Exit reason 0x%x", 1610 vmcb->control.exit_code); 1611 return true; 1612 } 1613 vmcb->save.rip += 3; 1614 report(count_exc == 1, "divide overflow exception injected"); 1615 report(!(vmcb->control.event_inj & SVM_EVTINJ_VALID), "eventinj.VALID cleared"); 1616 break; 1617 1618 default: 1619 return true; 1620 } 1621 1622 inc_test_stage(test); 1623 1624 return get_test_stage(test) == 3; 1625 } 1626 1627 static bool exc_inject_check(struct svm_test *test) 1628 { 1629 return count_exc == 1 && get_test_stage(test) == 3; 1630 } 1631 1632 static volatile bool virq_fired; 1633 1634 static void virq_isr(isr_regs_t *regs) 1635 { 1636 virq_fired = true; 1637 } 1638 1639 static void virq_inject_prepare(struct svm_test *test) 1640 { 1641 handle_irq(0xf1, virq_isr); 1642 default_prepare(test); 1643 vmcb->control.int_ctl = V_INTR_MASKING_MASK | V_IRQ_MASK | 1644 (0x0f << V_INTR_PRIO_SHIFT); // Set to the highest priority 1645 vmcb->control.int_vector = 0xf1; 1646 virq_fired = false; 1647 set_test_stage(test, 0); 1648 } 1649 1650 static void virq_inject_test(struct svm_test *test) 1651 { 1652 if (virq_fired) { 1653 report_fail("virtual interrupt fired before L2 sti"); 1654 set_test_stage(test, -1); 1655 vmmcall(); 1656 } 1657 1658 irq_enable(); 1659 asm volatile ("nop"); 1660 irq_disable(); 1661 1662 if (!virq_fired) { 1663 report_fail("virtual interrupt not fired after L2 sti"); 1664 set_test_stage(test, -1); 1665 } 1666 1667 vmmcall(); 1668 1669 if (virq_fired) { 1670 report_fail("virtual interrupt fired before L2 sti after VINTR intercept"); 1671 set_test_stage(test, -1); 1672 vmmcall(); 1673 } 1674 1675 irq_enable(); 1676 asm volatile ("nop"); 1677 irq_disable(); 1678 1679 if (!virq_fired) { 1680 report_fail("virtual interrupt not fired after return from VINTR intercept"); 1681 set_test_stage(test, -1); 1682 } 1683 1684 vmmcall(); 1685 1686 irq_enable(); 1687 asm volatile ("nop"); 1688 irq_disable(); 1689 1690 if (virq_fired) { 1691 report_fail("virtual interrupt fired when V_IRQ_PRIO less than V_TPR"); 1692 set_test_stage(test, -1); 1693 } 1694 1695 vmmcall(); 1696 vmmcall(); 1697 } 1698 1699 static bool virq_inject_finished(struct svm_test *test) 1700 { 1701 vmcb->save.rip += 3; 1702 1703 switch (get_test_stage(test)) { 1704 case 0: 1705 if (vmcb->control.exit_code != SVM_EXIT_VMMCALL) { 1706 report_fail("VMEXIT not due to vmmcall. Exit reason 0x%x", 1707 vmcb->control.exit_code); 1708 return true; 1709 } 1710 if (vmcb->control.int_ctl & V_IRQ_MASK) { 1711 report_fail("V_IRQ not cleared on VMEXIT after firing"); 1712 return true; 1713 } 1714 virq_fired = false; 1715 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR); 1716 vmcb->control.int_ctl = V_INTR_MASKING_MASK | V_IRQ_MASK | 1717 (0x0f << V_INTR_PRIO_SHIFT); 1718 break; 1719 1720 case 1: 1721 if (vmcb->control.exit_code != SVM_EXIT_VINTR) { 1722 report_fail("VMEXIT not due to vintr. Exit reason 0x%x", 1723 vmcb->control.exit_code); 1724 return true; 1725 } 1726 if (virq_fired) { 1727 report_fail("V_IRQ fired before SVM_EXIT_VINTR"); 1728 return true; 1729 } 1730 vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR); 1731 break; 1732 1733 case 2: 1734 if (vmcb->control.exit_code != SVM_EXIT_VMMCALL) { 1735 report_fail("VMEXIT not due to vmmcall. Exit reason 0x%x", 1736 vmcb->control.exit_code); 1737 return true; 1738 } 1739 virq_fired = false; 1740 // Set irq to lower priority 1741 vmcb->control.int_ctl = V_INTR_MASKING_MASK | V_IRQ_MASK | 1742 (0x08 << V_INTR_PRIO_SHIFT); 1743 // Raise guest TPR 1744 vmcb->control.int_ctl |= 0x0a & V_TPR_MASK; 1745 break; 1746 1747 case 3: 1748 if (vmcb->control.exit_code != SVM_EXIT_VMMCALL) { 1749 report_fail("VMEXIT not due to vmmcall. Exit reason 0x%x", 1750 vmcb->control.exit_code); 1751 return true; 1752 } 1753 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR); 1754 break; 1755 1756 case 4: 1757 // INTERCEPT_VINTR should be ignored because V_INTR_PRIO < V_TPR 1758 if (vmcb->control.exit_code != SVM_EXIT_VMMCALL) { 1759 report_fail("VMEXIT not due to vmmcall. Exit reason 0x%x", 1760 vmcb->control.exit_code); 1761 return true; 1762 } 1763 break; 1764 1765 default: 1766 return true; 1767 } 1768 1769 inc_test_stage(test); 1770 1771 return get_test_stage(test) == 5; 1772 } 1773 1774 static bool virq_inject_check(struct svm_test *test) 1775 { 1776 return get_test_stage(test) == 5; 1777 } 1778 1779 /* 1780 * Detect nested guest RIP corruption as explained in kernel commit 1781 * b6162e82aef19fee9c32cb3fe9ac30d9116a8c73 1782 * 1783 * In the assembly loop below 'ins' is executed while IO instructions 1784 * are not intercepted; the instruction is emulated by L0. 1785 * 1786 * At the same time we are getting interrupts from the local APIC timer, 1787 * and we do intercept them in L1 1788 * 1789 * If the interrupt happens on the insb instruction, L0 will VMexit, emulate 1790 * the insb instruction and then it will inject the interrupt to L1 through 1791 * a nested VMexit. Due to a bug, it would leave pre-emulation values of RIP, 1792 * RAX and RSP in the VMCB. 1793 * 1794 * In our intercept handler we detect the bug by checking that RIP is that of 1795 * the insb instruction, but its memory operand has already been written. 1796 * This means that insb was already executed. 1797 */ 1798 1799 static volatile int isr_cnt = 0; 1800 static volatile uint8_t io_port_var = 0xAA; 1801 extern const char insb_instruction_label[]; 1802 1803 static void reg_corruption_isr(isr_regs_t *regs) 1804 { 1805 isr_cnt++; 1806 apic_write(APIC_EOI, 0); 1807 } 1808 1809 static void reg_corruption_prepare(struct svm_test *test) 1810 { 1811 default_prepare(test); 1812 set_test_stage(test, 0); 1813 1814 vmcb->control.int_ctl = V_INTR_MASKING_MASK; 1815 vmcb->control.intercept |= (1ULL << INTERCEPT_INTR); 1816 1817 handle_irq(TIMER_VECTOR, reg_corruption_isr); 1818 1819 /* set local APIC to inject external interrupts */ 1820 apic_write(APIC_TMICT, 0); 1821 apic_write(APIC_TDCR, 0); 1822 apic_write(APIC_LVTT, TIMER_VECTOR | APIC_LVT_TIMER_PERIODIC); 1823 apic_write(APIC_TMICT, 1000); 1824 } 1825 1826 static void reg_corruption_test(struct svm_test *test) 1827 { 1828 /* this is endless loop, which is interrupted by the timer interrupt */ 1829 asm volatile ( 1830 "1:\n\t" 1831 "movw $0x4d0, %%dx\n\t" // IO port 1832 "lea %[io_port_var], %%rdi\n\t" 1833 "movb $0xAA, %[io_port_var]\n\t" 1834 "insb_instruction_label:\n\t" 1835 "insb\n\t" 1836 "jmp 1b\n\t" 1837 1838 : [io_port_var] "=m" (io_port_var) 1839 : /* no inputs*/ 1840 : "rdx", "rdi" 1841 ); 1842 } 1843 1844 static bool reg_corruption_finished(struct svm_test *test) 1845 { 1846 if (isr_cnt == 10000) { 1847 report_pass("No RIP corruption detected after %d timer interrupts", 1848 isr_cnt); 1849 set_test_stage(test, 1); 1850 return true; 1851 } 1852 1853 if (vmcb->control.exit_code == SVM_EXIT_INTR) { 1854 1855 void* guest_rip = (void*)vmcb->save.rip; 1856 1857 irq_enable(); 1858 asm volatile ("nop"); 1859 irq_disable(); 1860 1861 if (guest_rip == insb_instruction_label && io_port_var != 0xAA) { 1862 report_fail("RIP corruption detected after %d timer interrupts", 1863 isr_cnt); 1864 return true; 1865 } 1866 1867 } 1868 return false; 1869 } 1870 1871 static bool reg_corruption_check(struct svm_test *test) 1872 { 1873 return get_test_stage(test) == 1; 1874 } 1875 1876 static void get_tss_entry(void *data) 1877 { 1878 struct descriptor_table_ptr gdt; 1879 struct segment_desc64 *gdt_table; 1880 struct segment_desc64 *tss_entry; 1881 u16 tr = 0; 1882 1883 sgdt(&gdt); 1884 tr = str(); 1885 gdt_table = (struct segment_desc64 *) gdt.base; 1886 tss_entry = &gdt_table[tr / sizeof(struct segment_desc64)]; 1887 *((struct segment_desc64 **)data) = tss_entry; 1888 } 1889 1890 static int orig_cpu_count; 1891 1892 static void init_startup_prepare(struct svm_test *test) 1893 { 1894 struct segment_desc64 *tss_entry; 1895 int i; 1896 1897 on_cpu(1, get_tss_entry, &tss_entry); 1898 1899 orig_cpu_count = cpu_online_count; 1900 1901 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 1902 id_map[1]); 1903 1904 delay(100000000ULL); 1905 1906 --cpu_online_count; 1907 1908 *(uint64_t *)tss_entry &= ~DESC_BUSY; 1909 1910 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP, id_map[1]); 1911 1912 for (i = 0; i < 5 && cpu_online_count < orig_cpu_count; i++) 1913 delay(100000000ULL); 1914 } 1915 1916 static bool init_startup_finished(struct svm_test *test) 1917 { 1918 return true; 1919 } 1920 1921 static bool init_startup_check(struct svm_test *test) 1922 { 1923 return cpu_online_count == orig_cpu_count; 1924 } 1925 1926 static volatile bool init_intercept; 1927 1928 static void init_intercept_prepare(struct svm_test *test) 1929 { 1930 init_intercept = false; 1931 vmcb->control.intercept |= (1ULL << INTERCEPT_INIT); 1932 } 1933 1934 static void init_intercept_test(struct svm_test *test) 1935 { 1936 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 0); 1937 } 1938 1939 static bool init_intercept_finished(struct svm_test *test) 1940 { 1941 vmcb->save.rip += 3; 1942 1943 if (vmcb->control.exit_code != SVM_EXIT_INIT) { 1944 report_fail("VMEXIT not due to init intercept. Exit reason 0x%x", 1945 vmcb->control.exit_code); 1946 1947 return true; 1948 } 1949 1950 init_intercept = true; 1951 1952 report_pass("INIT to vcpu intercepted"); 1953 1954 return true; 1955 } 1956 1957 static bool init_intercept_check(struct svm_test *test) 1958 { 1959 return init_intercept; 1960 } 1961 1962 /* 1963 * Setting host EFLAGS.TF causes a #DB trap after the VMRUN completes on the 1964 * host side (i.e., after the #VMEXIT from the guest). 1965 * 1966 * Setting host EFLAGS.RF suppresses any potential instruction breakpoint 1967 * match on the VMRUN and completion of the VMRUN instruction clears the 1968 * host EFLAGS.RF bit. 1969 * 1970 * [AMD APM] 1971 */ 1972 static volatile u8 host_rflags_guest_main_flag = 0; 1973 static volatile u8 host_rflags_db_handler_flag = 0; 1974 static volatile bool host_rflags_ss_on_vmrun = false; 1975 static volatile bool host_rflags_vmrun_reached = false; 1976 static volatile bool host_rflags_set_tf = false; 1977 static volatile bool host_rflags_set_rf = false; 1978 static u64 rip_detected; 1979 1980 extern u64 *vmrun_rip; 1981 1982 static void host_rflags_db_handler(struct ex_regs *r) 1983 { 1984 if (host_rflags_ss_on_vmrun) { 1985 if (host_rflags_vmrun_reached) { 1986 if (!host_rflags_set_rf) { 1987 r->rflags &= ~X86_EFLAGS_TF; 1988 rip_detected = r->rip; 1989 } else { 1990 r->rflags |= X86_EFLAGS_RF; 1991 ++host_rflags_db_handler_flag; 1992 } 1993 } else { 1994 if (r->rip == (u64)&vmrun_rip) { 1995 host_rflags_vmrun_reached = true; 1996 1997 if (host_rflags_set_rf) { 1998 host_rflags_guest_main_flag = 0; 1999 rip_detected = r->rip; 2000 r->rflags &= ~X86_EFLAGS_TF; 2001 2002 /* Trigger #DB via debug registers */ 2003 write_dr0((void *)&vmrun_rip); 2004 write_dr7(0x403); 2005 } 2006 } 2007 } 2008 } else { 2009 r->rflags &= ~X86_EFLAGS_TF; 2010 } 2011 } 2012 2013 static void host_rflags_prepare(struct svm_test *test) 2014 { 2015 default_prepare(test); 2016 handle_exception(DB_VECTOR, host_rflags_db_handler); 2017 set_test_stage(test, 0); 2018 } 2019 2020 static void host_rflags_prepare_gif_clear(struct svm_test *test) 2021 { 2022 if (host_rflags_set_tf) 2023 write_rflags(read_rflags() | X86_EFLAGS_TF); 2024 } 2025 2026 static void host_rflags_test(struct svm_test *test) 2027 { 2028 while (1) { 2029 if (get_test_stage(test) > 0) { 2030 if ((host_rflags_set_tf && !host_rflags_ss_on_vmrun && !host_rflags_db_handler_flag) || 2031 (host_rflags_set_rf && host_rflags_db_handler_flag == 1)) 2032 host_rflags_guest_main_flag = 1; 2033 } 2034 2035 if (get_test_stage(test) == 4) 2036 break; 2037 vmmcall(); 2038 } 2039 } 2040 2041 static bool host_rflags_finished(struct svm_test *test) 2042 { 2043 switch (get_test_stage(test)) { 2044 case 0: 2045 if (vmcb->control.exit_code != SVM_EXIT_VMMCALL) { 2046 report_fail("Unexpected VMEXIT. Exit reason 0x%x", 2047 vmcb->control.exit_code); 2048 return true; 2049 } 2050 vmcb->save.rip += 3; 2051 /* 2052 * Setting host EFLAGS.TF not immediately before VMRUN, causes 2053 * #DB trap before first guest instruction is executed 2054 */ 2055 host_rflags_set_tf = true; 2056 break; 2057 case 1: 2058 if (vmcb->control.exit_code != SVM_EXIT_VMMCALL || 2059 host_rflags_guest_main_flag != 1) { 2060 report_fail("Unexpected VMEXIT or #DB handler" 2061 " invoked before guest main. Exit reason 0x%x", 2062 vmcb->control.exit_code); 2063 return true; 2064 } 2065 vmcb->save.rip += 3; 2066 /* 2067 * Setting host EFLAGS.TF immediately before VMRUN, causes #DB 2068 * trap after VMRUN completes on the host side (i.e., after 2069 * VMEXIT from guest). 2070 */ 2071 host_rflags_ss_on_vmrun = true; 2072 break; 2073 case 2: 2074 if (vmcb->control.exit_code != SVM_EXIT_VMMCALL || 2075 rip_detected != (u64)&vmrun_rip + 3) { 2076 report_fail("Unexpected VMEXIT or RIP mismatch." 2077 " Exit reason 0x%x, RIP actual: %lx, RIP expected: " 2078 "%lx", vmcb->control.exit_code, 2079 (u64)&vmrun_rip + 3, rip_detected); 2080 return true; 2081 } 2082 host_rflags_set_rf = true; 2083 host_rflags_guest_main_flag = 0; 2084 host_rflags_vmrun_reached = false; 2085 vmcb->save.rip += 3; 2086 break; 2087 case 3: 2088 if (vmcb->control.exit_code != SVM_EXIT_VMMCALL || 2089 rip_detected != (u64)&vmrun_rip || 2090 host_rflags_guest_main_flag != 1 || 2091 host_rflags_db_handler_flag > 1 || 2092 read_rflags() & X86_EFLAGS_RF) { 2093 report_fail("Unexpected VMEXIT or RIP mismatch or " 2094 "EFLAGS.RF not cleared." 2095 " Exit reason 0x%x, RIP actual: %lx, RIP expected: " 2096 "%lx", vmcb->control.exit_code, 2097 (u64)&vmrun_rip, rip_detected); 2098 return true; 2099 } 2100 host_rflags_set_tf = false; 2101 host_rflags_set_rf = false; 2102 vmcb->save.rip += 3; 2103 break; 2104 default: 2105 return true; 2106 } 2107 inc_test_stage(test); 2108 return get_test_stage(test) == 5; 2109 } 2110 2111 static bool host_rflags_check(struct svm_test *test) 2112 { 2113 return get_test_stage(test) == 4; 2114 } 2115 2116 #define TEST(name) { #name, .v2 = name } 2117 2118 /* 2119 * v2 tests 2120 */ 2121 2122 /* 2123 * Ensure that kvm recalculates the L1 guest's CPUID.01H:ECX.OSXSAVE 2124 * after VM-exit from an L2 guest that sets CR4.OSXSAVE to a different 2125 * value than in L1. 2126 */ 2127 2128 static void svm_cr4_osxsave_test_guest(struct svm_test *test) 2129 { 2130 write_cr4(read_cr4() & ~X86_CR4_OSXSAVE); 2131 } 2132 2133 static void svm_cr4_osxsave_test(void) 2134 { 2135 if (!this_cpu_has(X86_FEATURE_XSAVE)) { 2136 report_skip("XSAVE not detected"); 2137 return; 2138 } 2139 2140 if (!(read_cr4() & X86_CR4_OSXSAVE)) { 2141 unsigned long cr4 = read_cr4() | X86_CR4_OSXSAVE; 2142 2143 write_cr4(cr4); 2144 vmcb->save.cr4 = cr4; 2145 } 2146 2147 report(cpuid_osxsave(), "CPUID.01H:ECX.XSAVE set before VMRUN"); 2148 2149 test_set_guest(svm_cr4_osxsave_test_guest); 2150 report(svm_vmrun() == SVM_EXIT_VMMCALL, 2151 "svm_cr4_osxsave_test_guest finished with VMMCALL"); 2152 2153 report(cpuid_osxsave(), "CPUID.01H:ECX.XSAVE set after VMRUN"); 2154 } 2155 2156 static void basic_guest_main(struct svm_test *test) 2157 { 2158 } 2159 2160 2161 #define SVM_TEST_REG_RESERVED_BITS(start, end, inc, str_name, reg, val, \ 2162 resv_mask) \ 2163 { \ 2164 u64 tmp, mask; \ 2165 int i; \ 2166 \ 2167 for (i = start; i <= end; i = i + inc) { \ 2168 mask = 1ull << i; \ 2169 if (!(mask & resv_mask)) \ 2170 continue; \ 2171 tmp = val | mask; \ 2172 reg = tmp; \ 2173 report(svm_vmrun() == SVM_EXIT_ERR, "Test %s %d:%d: %lx",\ 2174 str_name, end, start, tmp); \ 2175 } \ 2176 } 2177 2178 #define SVM_TEST_CR_RESERVED_BITS(start, end, inc, cr, val, resv_mask, \ 2179 exit_code, test_name) \ 2180 { \ 2181 u64 tmp, mask; \ 2182 u32 r; \ 2183 int i; \ 2184 \ 2185 for (i = start; i <= end; i = i + inc) { \ 2186 mask = 1ull << i; \ 2187 if (!(mask & resv_mask)) \ 2188 continue; \ 2189 tmp = val | mask; \ 2190 switch (cr) { \ 2191 case 0: \ 2192 vmcb->save.cr0 = tmp; \ 2193 break; \ 2194 case 3: \ 2195 vmcb->save.cr3 = tmp; \ 2196 break; \ 2197 case 4: \ 2198 vmcb->save.cr4 = tmp; \ 2199 } \ 2200 r = svm_vmrun(); \ 2201 report(r == exit_code, "Test CR%d %s%d:%d: %lx, wanted exit 0x%x, got 0x%x",\ 2202 cr, test_name, end, start, tmp, exit_code, r); \ 2203 } \ 2204 } 2205 2206 static void test_efer(void) 2207 { 2208 /* 2209 * Un-setting EFER.SVME is illegal 2210 */ 2211 u64 efer_saved = vmcb->save.efer; 2212 u64 efer = efer_saved; 2213 2214 report (svm_vmrun() == SVM_EXIT_VMMCALL, "EFER.SVME: %lx", efer); 2215 efer &= ~EFER_SVME; 2216 vmcb->save.efer = efer; 2217 report (svm_vmrun() == SVM_EXIT_ERR, "EFER.SVME: %lx", efer); 2218 vmcb->save.efer = efer_saved; 2219 2220 /* 2221 * EFER MBZ bits: 63:16, 9 2222 */ 2223 efer_saved = vmcb->save.efer; 2224 2225 SVM_TEST_REG_RESERVED_BITS(8, 9, 1, "EFER", vmcb->save.efer, 2226 efer_saved, SVM_EFER_RESERVED_MASK); 2227 SVM_TEST_REG_RESERVED_BITS(16, 63, 4, "EFER", vmcb->save.efer, 2228 efer_saved, SVM_EFER_RESERVED_MASK); 2229 2230 /* 2231 * EFER.LME and CR0.PG are both set and CR4.PAE is zero. 2232 */ 2233 u64 cr0_saved = vmcb->save.cr0; 2234 u64 cr0; 2235 u64 cr4_saved = vmcb->save.cr4; 2236 u64 cr4; 2237 2238 efer = efer_saved | EFER_LME; 2239 vmcb->save.efer = efer; 2240 cr0 = cr0_saved | X86_CR0_PG | X86_CR0_PE; 2241 vmcb->save.cr0 = cr0; 2242 cr4 = cr4_saved & ~X86_CR4_PAE; 2243 vmcb->save.cr4 = cr4; 2244 report(svm_vmrun() == SVM_EXIT_ERR, "EFER.LME=1 (%lx), " 2245 "CR0.PG=1 (%lx) and CR4.PAE=0 (%lx)", efer, cr0, cr4); 2246 2247 /* 2248 * EFER.LME and CR0.PG are both set and CR0.PE is zero. 2249 * CR4.PAE needs to be set as we otherwise cannot 2250 * determine if CR4.PAE=0 or CR0.PE=0 triggered the 2251 * SVM_EXIT_ERR. 2252 */ 2253 cr4 = cr4_saved | X86_CR4_PAE; 2254 vmcb->save.cr4 = cr4; 2255 cr0 &= ~X86_CR0_PE; 2256 vmcb->save.cr0 = cr0; 2257 report(svm_vmrun() == SVM_EXIT_ERR, "EFER.LME=1 (%lx), " 2258 "CR0.PG=1 and CR0.PE=0 (%lx)", efer, cr0); 2259 2260 /* 2261 * EFER.LME, CR0.PG, CR4.PAE, CS.L, and CS.D are all non-zero. 2262 */ 2263 u32 cs_attrib_saved = vmcb->save.cs.attrib; 2264 u32 cs_attrib; 2265 2266 cr0 |= X86_CR0_PE; 2267 vmcb->save.cr0 = cr0; 2268 cs_attrib = cs_attrib_saved | SVM_SELECTOR_L_MASK | 2269 SVM_SELECTOR_DB_MASK; 2270 vmcb->save.cs.attrib = cs_attrib; 2271 report(svm_vmrun() == SVM_EXIT_ERR, "EFER.LME=1 (%lx), " 2272 "CR0.PG=1 (%lx), CR4.PAE=1 (%lx), CS.L=1 and CS.D=1 (%x)", 2273 efer, cr0, cr4, cs_attrib); 2274 2275 vmcb->save.cr0 = cr0_saved; 2276 vmcb->save.cr4 = cr4_saved; 2277 vmcb->save.efer = efer_saved; 2278 vmcb->save.cs.attrib = cs_attrib_saved; 2279 } 2280 2281 static void test_cr0(void) 2282 { 2283 /* 2284 * Un-setting CR0.CD and setting CR0.NW is illegal combination 2285 */ 2286 u64 cr0_saved = vmcb->save.cr0; 2287 u64 cr0 = cr0_saved; 2288 2289 cr0 |= X86_CR0_CD; 2290 cr0 &= ~X86_CR0_NW; 2291 vmcb->save.cr0 = cr0; 2292 report (svm_vmrun() == SVM_EXIT_VMMCALL, "Test CR0 CD=1,NW=0: %lx", 2293 cr0); 2294 cr0 |= X86_CR0_NW; 2295 vmcb->save.cr0 = cr0; 2296 report (svm_vmrun() == SVM_EXIT_VMMCALL, "Test CR0 CD=1,NW=1: %lx", 2297 cr0); 2298 cr0 &= ~X86_CR0_NW; 2299 cr0 &= ~X86_CR0_CD; 2300 vmcb->save.cr0 = cr0; 2301 report (svm_vmrun() == SVM_EXIT_VMMCALL, "Test CR0 CD=0,NW=0: %lx", 2302 cr0); 2303 cr0 |= X86_CR0_NW; 2304 vmcb->save.cr0 = cr0; 2305 report (svm_vmrun() == SVM_EXIT_ERR, "Test CR0 CD=0,NW=1: %lx", 2306 cr0); 2307 vmcb->save.cr0 = cr0_saved; 2308 2309 /* 2310 * CR0[63:32] are not zero 2311 */ 2312 cr0 = cr0_saved; 2313 2314 SVM_TEST_REG_RESERVED_BITS(32, 63, 4, "CR0", vmcb->save.cr0, cr0_saved, 2315 SVM_CR0_RESERVED_MASK); 2316 vmcb->save.cr0 = cr0_saved; 2317 } 2318 2319 static void test_cr3(void) 2320 { 2321 /* 2322 * CR3 MBZ bits based on different modes: 2323 * [63:52] - long mode 2324 */ 2325 u64 cr3_saved = vmcb->save.cr3; 2326 2327 SVM_TEST_CR_RESERVED_BITS(0, 63, 1, 3, cr3_saved, 2328 SVM_CR3_LONG_MBZ_MASK, SVM_EXIT_ERR, ""); 2329 2330 vmcb->save.cr3 = cr3_saved & ~SVM_CR3_LONG_MBZ_MASK; 2331 report(svm_vmrun() == SVM_EXIT_VMMCALL, "Test CR3 63:0: %lx", 2332 vmcb->save.cr3); 2333 2334 /* 2335 * CR3 non-MBZ reserved bits based on different modes: 2336 * [11:5] [2:0] - long mode (PCIDE=0) 2337 * [2:0] - PAE legacy mode 2338 */ 2339 u64 cr4_saved = vmcb->save.cr4; 2340 u64 *pdpe = npt_get_pml4e(); 2341 2342 /* 2343 * Long mode 2344 */ 2345 if (this_cpu_has(X86_FEATURE_PCID)) { 2346 vmcb->save.cr4 = cr4_saved | X86_CR4_PCIDE; 2347 SVM_TEST_CR_RESERVED_BITS(0, 11, 1, 3, cr3_saved, 2348 SVM_CR3_LONG_RESERVED_MASK, SVM_EXIT_VMMCALL, "(PCIDE=1) "); 2349 2350 vmcb->save.cr3 = cr3_saved & ~SVM_CR3_LONG_RESERVED_MASK; 2351 report(svm_vmrun() == SVM_EXIT_VMMCALL, "Test CR3 63:0: %lx", 2352 vmcb->save.cr3); 2353 } 2354 2355 vmcb->save.cr4 = cr4_saved & ~X86_CR4_PCIDE; 2356 2357 if (!npt_supported()) 2358 goto skip_npt_only; 2359 2360 /* Clear P (Present) bit in NPT in order to trigger #NPF */ 2361 pdpe[0] &= ~1ULL; 2362 2363 SVM_TEST_CR_RESERVED_BITS(0, 11, 1, 3, cr3_saved, 2364 SVM_CR3_LONG_RESERVED_MASK, SVM_EXIT_NPF, "(PCIDE=0) "); 2365 2366 pdpe[0] |= 1ULL; 2367 vmcb->save.cr3 = cr3_saved; 2368 2369 /* 2370 * PAE legacy 2371 */ 2372 pdpe[0] &= ~1ULL; 2373 vmcb->save.cr4 = cr4_saved | X86_CR4_PAE; 2374 SVM_TEST_CR_RESERVED_BITS(0, 2, 1, 3, cr3_saved, 2375 SVM_CR3_PAE_LEGACY_RESERVED_MASK, SVM_EXIT_NPF, "(PAE) "); 2376 2377 pdpe[0] |= 1ULL; 2378 2379 skip_npt_only: 2380 vmcb->save.cr3 = cr3_saved; 2381 vmcb->save.cr4 = cr4_saved; 2382 } 2383 2384 /* Test CR4 MBZ bits based on legacy or long modes */ 2385 static void test_cr4(void) 2386 { 2387 u64 cr4_saved = vmcb->save.cr4; 2388 u64 efer_saved = vmcb->save.efer; 2389 u64 efer = efer_saved; 2390 2391 efer &= ~EFER_LME; 2392 vmcb->save.efer = efer; 2393 SVM_TEST_CR_RESERVED_BITS(12, 31, 1, 4, cr4_saved, 2394 SVM_CR4_LEGACY_RESERVED_MASK, SVM_EXIT_ERR, ""); 2395 2396 efer |= EFER_LME; 2397 vmcb->save.efer = efer; 2398 SVM_TEST_CR_RESERVED_BITS(12, 31, 1, 4, cr4_saved, 2399 SVM_CR4_RESERVED_MASK, SVM_EXIT_ERR, ""); 2400 SVM_TEST_CR_RESERVED_BITS(32, 63, 4, 4, cr4_saved, 2401 SVM_CR4_RESERVED_MASK, SVM_EXIT_ERR, ""); 2402 2403 vmcb->save.cr4 = cr4_saved; 2404 vmcb->save.efer = efer_saved; 2405 } 2406 2407 static void test_dr(void) 2408 { 2409 /* 2410 * DR6[63:32] and DR7[63:32] are MBZ 2411 */ 2412 u64 dr_saved = vmcb->save.dr6; 2413 2414 SVM_TEST_REG_RESERVED_BITS(32, 63, 4, "DR6", vmcb->save.dr6, dr_saved, 2415 SVM_DR6_RESERVED_MASK); 2416 vmcb->save.dr6 = dr_saved; 2417 2418 dr_saved = vmcb->save.dr7; 2419 SVM_TEST_REG_RESERVED_BITS(32, 63, 4, "DR7", vmcb->save.dr7, dr_saved, 2420 SVM_DR7_RESERVED_MASK); 2421 2422 vmcb->save.dr7 = dr_saved; 2423 } 2424 2425 /* TODO: verify if high 32-bits are sign- or zero-extended on bare metal */ 2426 #define TEST_BITMAP_ADDR(save_intercept, type, addr, exit_code, \ 2427 msg) { \ 2428 vmcb->control.intercept = saved_intercept | 1ULL << type; \ 2429 if (type == INTERCEPT_MSR_PROT) \ 2430 vmcb->control.msrpm_base_pa = addr; \ 2431 else \ 2432 vmcb->control.iopm_base_pa = addr; \ 2433 report(svm_vmrun() == exit_code, \ 2434 "Test %s address: %lx", msg, addr); \ 2435 } 2436 2437 /* 2438 * If the MSR or IOIO intercept table extends to a physical address that 2439 * is greater than or equal to the maximum supported physical address, the 2440 * guest state is illegal. 2441 * 2442 * The VMRUN instruction ignores the lower 12 bits of the address specified 2443 * in the VMCB. 2444 * 2445 * MSRPM spans 2 contiguous 4KB pages while IOPM spans 2 contiguous 4KB 2446 * pages + 1 byte. 2447 * 2448 * [APM vol 2] 2449 * 2450 * Note: Unallocated MSRPM addresses conforming to consistency checks, generate 2451 * #NPF. 2452 */ 2453 static void test_msrpm_iopm_bitmap_addrs(void) 2454 { 2455 u64 saved_intercept = vmcb->control.intercept; 2456 u64 addr_beyond_limit = 1ull << cpuid_maxphyaddr(); 2457 u64 addr = virt_to_phys(msr_bitmap) & (~((1ull << 12) - 1)); 2458 2459 TEST_BITMAP_ADDR(saved_intercept, INTERCEPT_MSR_PROT, 2460 addr_beyond_limit - 2 * PAGE_SIZE, SVM_EXIT_ERR, 2461 "MSRPM"); 2462 TEST_BITMAP_ADDR(saved_intercept, INTERCEPT_MSR_PROT, 2463 addr_beyond_limit - 2 * PAGE_SIZE + 1, SVM_EXIT_ERR, 2464 "MSRPM"); 2465 TEST_BITMAP_ADDR(saved_intercept, INTERCEPT_MSR_PROT, 2466 addr_beyond_limit - PAGE_SIZE, SVM_EXIT_ERR, 2467 "MSRPM"); 2468 TEST_BITMAP_ADDR(saved_intercept, INTERCEPT_MSR_PROT, addr, 2469 SVM_EXIT_VMMCALL, "MSRPM"); 2470 addr |= (1ull << 12) - 1; 2471 TEST_BITMAP_ADDR(saved_intercept, INTERCEPT_MSR_PROT, addr, 2472 SVM_EXIT_VMMCALL, "MSRPM"); 2473 2474 TEST_BITMAP_ADDR(saved_intercept, INTERCEPT_IOIO_PROT, 2475 addr_beyond_limit - 4 * PAGE_SIZE, SVM_EXIT_VMMCALL, 2476 "IOPM"); 2477 TEST_BITMAP_ADDR(saved_intercept, INTERCEPT_IOIO_PROT, 2478 addr_beyond_limit - 3 * PAGE_SIZE, SVM_EXIT_VMMCALL, 2479 "IOPM"); 2480 TEST_BITMAP_ADDR(saved_intercept, INTERCEPT_IOIO_PROT, 2481 addr_beyond_limit - 2 * PAGE_SIZE - 2, SVM_EXIT_VMMCALL, 2482 "IOPM"); 2483 TEST_BITMAP_ADDR(saved_intercept, INTERCEPT_IOIO_PROT, 2484 addr_beyond_limit - 2 * PAGE_SIZE, SVM_EXIT_ERR, 2485 "IOPM"); 2486 TEST_BITMAP_ADDR(saved_intercept, INTERCEPT_IOIO_PROT, 2487 addr_beyond_limit - PAGE_SIZE, SVM_EXIT_ERR, 2488 "IOPM"); 2489 addr = virt_to_phys(io_bitmap) & (~((1ull << 11) - 1)); 2490 TEST_BITMAP_ADDR(saved_intercept, INTERCEPT_IOIO_PROT, addr, 2491 SVM_EXIT_VMMCALL, "IOPM"); 2492 addr |= (1ull << 12) - 1; 2493 TEST_BITMAP_ADDR(saved_intercept, INTERCEPT_IOIO_PROT, addr, 2494 SVM_EXIT_VMMCALL, "IOPM"); 2495 2496 vmcb->control.intercept = saved_intercept; 2497 } 2498 2499 /* 2500 * Unlike VMSAVE, VMRUN seems not to update the value of noncanonical 2501 * segment bases in the VMCB. However, VMENTRY succeeds as documented. 2502 */ 2503 #define TEST_CANONICAL_VMRUN(seg_base, msg) \ 2504 saved_addr = seg_base; \ 2505 seg_base = (seg_base & ((1ul << addr_limit) - 1)) | noncanonical_mask; \ 2506 return_value = svm_vmrun(); \ 2507 report(return_value == SVM_EXIT_VMMCALL, \ 2508 "Successful VMRUN with noncanonical %s.base", msg); \ 2509 seg_base = saved_addr; 2510 2511 2512 #define TEST_CANONICAL_VMLOAD(seg_base, msg) \ 2513 saved_addr = seg_base; \ 2514 seg_base = (seg_base & ((1ul << addr_limit) - 1)) | noncanonical_mask; \ 2515 asm volatile ("vmload %0" : : "a"(vmcb_phys) : "memory"); \ 2516 asm volatile ("vmsave %0" : : "a"(vmcb_phys) : "memory"); \ 2517 report(is_canonical(seg_base), \ 2518 "Test %s.base for canonical form: %lx", msg, seg_base); \ 2519 seg_base = saved_addr; 2520 2521 static void test_canonicalization(void) 2522 { 2523 u64 saved_addr; 2524 u64 return_value; 2525 u64 addr_limit; 2526 u64 vmcb_phys = virt_to_phys(vmcb); 2527 2528 addr_limit = (this_cpu_has(X86_FEATURE_LA57)) ? 57 : 48; 2529 u64 noncanonical_mask = NONCANONICAL & ~((1ul << addr_limit) - 1); 2530 2531 TEST_CANONICAL_VMLOAD(vmcb->save.fs.base, "FS"); 2532 TEST_CANONICAL_VMLOAD(vmcb->save.gs.base, "GS"); 2533 TEST_CANONICAL_VMLOAD(vmcb->save.ldtr.base, "LDTR"); 2534 TEST_CANONICAL_VMLOAD(vmcb->save.tr.base, "TR"); 2535 TEST_CANONICAL_VMLOAD(vmcb->save.kernel_gs_base, "KERNEL GS"); 2536 TEST_CANONICAL_VMRUN(vmcb->save.es.base, "ES"); 2537 TEST_CANONICAL_VMRUN(vmcb->save.cs.base, "CS"); 2538 TEST_CANONICAL_VMRUN(vmcb->save.ss.base, "SS"); 2539 TEST_CANONICAL_VMRUN(vmcb->save.ds.base, "DS"); 2540 TEST_CANONICAL_VMRUN(vmcb->save.gdtr.base, "GDTR"); 2541 TEST_CANONICAL_VMRUN(vmcb->save.idtr.base, "IDTR"); 2542 } 2543 2544 /* 2545 * When VMRUN loads a guest value of 1 in EFLAGS.TF, that value does not 2546 * cause a trace trap between the VMRUN and the first guest instruction, but 2547 * rather after completion of the first guest instruction. 2548 * 2549 * [APM vol 2] 2550 */ 2551 u64 guest_rflags_test_trap_rip; 2552 2553 static void guest_rflags_test_db_handler(struct ex_regs *r) 2554 { 2555 guest_rflags_test_trap_rip = r->rip; 2556 r->rflags &= ~X86_EFLAGS_TF; 2557 } 2558 2559 static void svm_guest_state_test(void) 2560 { 2561 test_set_guest(basic_guest_main); 2562 test_efer(); 2563 test_cr0(); 2564 test_cr3(); 2565 test_cr4(); 2566 test_dr(); 2567 test_msrpm_iopm_bitmap_addrs(); 2568 test_canonicalization(); 2569 } 2570 2571 extern void guest_rflags_test_guest(struct svm_test *test); 2572 extern u64 *insn2; 2573 extern u64 *guest_end; 2574 2575 asm("guest_rflags_test_guest:\n\t" 2576 "push %rbp\n\t" 2577 ".global insn2\n\t" 2578 "insn2:\n\t" 2579 "mov %rsp,%rbp\n\t" 2580 "vmmcall\n\t" 2581 "vmmcall\n\t" 2582 ".global guest_end\n\t" 2583 "guest_end:\n\t" 2584 "vmmcall\n\t" 2585 "pop %rbp\n\t" 2586 "ret"); 2587 2588 static void svm_test_singlestep(void) 2589 { 2590 handle_exception(DB_VECTOR, guest_rflags_test_db_handler); 2591 2592 /* 2593 * Trap expected after completion of first guest instruction 2594 */ 2595 vmcb->save.rflags |= X86_EFLAGS_TF; 2596 report (__svm_vmrun((u64)guest_rflags_test_guest) == SVM_EXIT_VMMCALL && 2597 guest_rflags_test_trap_rip == (u64)&insn2, 2598 "Test EFLAGS.TF on VMRUN: trap expected after completion of first guest instruction"); 2599 /* 2600 * No trap expected 2601 */ 2602 guest_rflags_test_trap_rip = 0; 2603 vmcb->save.rip += 3; 2604 vmcb->save.rflags |= X86_EFLAGS_TF; 2605 report (__svm_vmrun(vmcb->save.rip) == SVM_EXIT_VMMCALL && 2606 guest_rflags_test_trap_rip == 0, "Test EFLAGS.TF on VMRUN: trap not expected"); 2607 2608 /* 2609 * Let guest finish execution 2610 */ 2611 vmcb->save.rip += 3; 2612 report (__svm_vmrun(vmcb->save.rip) == SVM_EXIT_VMMCALL && 2613 vmcb->save.rip == (u64)&guest_end, "Test EFLAGS.TF on VMRUN: guest execution completion"); 2614 } 2615 2616 static void __svm_npt_rsvd_bits_test(u64 *pxe, u64 rsvd_bits, u64 efer, 2617 ulong cr4, u64 guest_efer, ulong guest_cr4) 2618 { 2619 u64 pxe_orig = *pxe; 2620 int exit_reason; 2621 u64 pfec; 2622 2623 wrmsr(MSR_EFER, efer); 2624 write_cr4(cr4); 2625 2626 vmcb->save.efer = guest_efer; 2627 vmcb->save.cr4 = guest_cr4; 2628 2629 *pxe |= rsvd_bits; 2630 2631 exit_reason = svm_vmrun(); 2632 2633 report(exit_reason == SVM_EXIT_NPF, 2634 "Wanted #NPF on rsvd bits = 0x%lx, got exit = 0x%x", rsvd_bits, exit_reason); 2635 2636 if (pxe == npt_get_pdpe() || pxe == npt_get_pml4e()) { 2637 /* 2638 * The guest's page tables will blow up on a bad PDPE/PML4E, 2639 * before starting the final walk of the guest page. 2640 */ 2641 pfec = 0x20000000full; 2642 } else { 2643 /* RSVD #NPF on final walk of guest page. */ 2644 pfec = 0x10000000dULL; 2645 2646 /* PFEC.FETCH=1 if NX=1 *or* SMEP=1. */ 2647 if ((cr4 & X86_CR4_SMEP) || (efer & EFER_NX)) 2648 pfec |= 0x10; 2649 2650 } 2651 2652 report(vmcb->control.exit_info_1 == pfec, 2653 "Wanted PFEC = 0x%lx, got PFEC = %lx, PxE = 0x%lx. " 2654 "host.NX = %u, host.SMEP = %u, guest.NX = %u, guest.SMEP = %u", 2655 pfec, vmcb->control.exit_info_1, *pxe, 2656 !!(efer & EFER_NX), !!(cr4 & X86_CR4_SMEP), 2657 !!(guest_efer & EFER_NX), !!(guest_cr4 & X86_CR4_SMEP)); 2658 2659 *pxe = pxe_orig; 2660 } 2661 2662 static void _svm_npt_rsvd_bits_test(u64 *pxe, u64 pxe_rsvd_bits, u64 efer, 2663 ulong cr4, u64 guest_efer, ulong guest_cr4) 2664 { 2665 u64 rsvd_bits; 2666 int i; 2667 2668 /* 2669 * RDTSC or RDRAND can sometimes fail to generate a valid reserved bits 2670 */ 2671 if (!pxe_rsvd_bits) { 2672 report_skip("svm_npt_rsvd_bits_test: Reserved bits are not valid"); 2673 return; 2674 } 2675 2676 /* 2677 * Test all combinations of guest/host EFER.NX and CR4.SMEP. If host 2678 * EFER.NX=0, use NX as the reserved bit, otherwise use the passed in 2679 * @pxe_rsvd_bits. 2680 */ 2681 for (i = 0; i < 16; i++) { 2682 if (i & 1) { 2683 rsvd_bits = pxe_rsvd_bits; 2684 efer |= EFER_NX; 2685 } else { 2686 rsvd_bits = PT64_NX_MASK; 2687 efer &= ~EFER_NX; 2688 } 2689 if (i & 2) 2690 cr4 |= X86_CR4_SMEP; 2691 else 2692 cr4 &= ~X86_CR4_SMEP; 2693 if (i & 4) 2694 guest_efer |= EFER_NX; 2695 else 2696 guest_efer &= ~EFER_NX; 2697 if (i & 8) 2698 guest_cr4 |= X86_CR4_SMEP; 2699 else 2700 guest_cr4 &= ~X86_CR4_SMEP; 2701 2702 __svm_npt_rsvd_bits_test(pxe, rsvd_bits, efer, cr4, 2703 guest_efer, guest_cr4); 2704 } 2705 } 2706 2707 static u64 get_random_bits(u64 hi, u64 low) 2708 { 2709 unsigned retry = 5; 2710 u64 rsvd_bits = 0; 2711 2712 if (this_cpu_has(X86_FEATURE_RDRAND)) { 2713 do { 2714 rsvd_bits = (rdrand() << low) & GENMASK_ULL(hi, low); 2715 retry--; 2716 } while (!rsvd_bits && retry); 2717 } 2718 2719 if (!rsvd_bits) { 2720 retry = 5; 2721 do { 2722 rsvd_bits = (rdtsc() << low) & GENMASK_ULL(hi, low); 2723 retry--; 2724 } while (!rsvd_bits && retry); 2725 } 2726 2727 return rsvd_bits; 2728 } 2729 2730 2731 static void svm_npt_rsvd_bits_test(void) 2732 { 2733 u64 saved_efer, host_efer, sg_efer, guest_efer; 2734 ulong saved_cr4, host_cr4, sg_cr4, guest_cr4; 2735 2736 if (!npt_supported()) { 2737 report_skip("NPT not supported"); 2738 return; 2739 } 2740 2741 saved_efer = host_efer = rdmsr(MSR_EFER); 2742 saved_cr4 = host_cr4 = read_cr4(); 2743 sg_efer = guest_efer = vmcb->save.efer; 2744 sg_cr4 = guest_cr4 = vmcb->save.cr4; 2745 2746 test_set_guest(basic_guest_main); 2747 2748 /* 2749 * 4k PTEs don't have reserved bits if MAXPHYADDR >= 52, just skip the 2750 * sub-test. The NX test is still valid, but the extra bit of coverage 2751 * isn't worth the extra complexity. 2752 */ 2753 if (cpuid_maxphyaddr() >= 52) 2754 goto skip_pte_test; 2755 2756 _svm_npt_rsvd_bits_test(npt_get_pte((u64)basic_guest_main), 2757 get_random_bits(51, cpuid_maxphyaddr()), 2758 host_efer, host_cr4, guest_efer, guest_cr4); 2759 2760 skip_pte_test: 2761 _svm_npt_rsvd_bits_test(npt_get_pde((u64)basic_guest_main), 2762 get_random_bits(20, 13) | PT_PAGE_SIZE_MASK, 2763 host_efer, host_cr4, guest_efer, guest_cr4); 2764 2765 _svm_npt_rsvd_bits_test(npt_get_pdpe(), 2766 PT_PAGE_SIZE_MASK | 2767 (this_cpu_has(X86_FEATURE_GBPAGES) ? get_random_bits(29, 13) : 0), 2768 host_efer, host_cr4, guest_efer, guest_cr4); 2769 2770 _svm_npt_rsvd_bits_test(npt_get_pml4e(), BIT_ULL(8), 2771 host_efer, host_cr4, guest_efer, guest_cr4); 2772 2773 wrmsr(MSR_EFER, saved_efer); 2774 write_cr4(saved_cr4); 2775 vmcb->save.efer = sg_efer; 2776 vmcb->save.cr4 = sg_cr4; 2777 } 2778 2779 static bool volatile svm_errata_reproduced = false; 2780 static unsigned long volatile physical = 0; 2781 2782 2783 /* 2784 * 2785 * Test the following errata: 2786 * If the VMRUN/VMSAVE/VMLOAD are attempted by the nested guest, 2787 * the CPU would first check the EAX against host reserved memory 2788 * regions (so far only SMM_ADDR/SMM_MASK are known to cause it), 2789 * and only then signal #VMexit 2790 * 2791 * Try to reproduce this by trying vmsave on each possible 4K aligned memory 2792 * address in the low 4G where the SMM area has to reside. 2793 */ 2794 2795 static void gp_isr(struct ex_regs *r) 2796 { 2797 svm_errata_reproduced = true; 2798 /* skip over the vmsave instruction*/ 2799 r->rip += 3; 2800 } 2801 2802 static void svm_vmrun_errata_test(void) 2803 { 2804 unsigned long *last_page = NULL; 2805 2806 handle_exception(GP_VECTOR, gp_isr); 2807 2808 while (!svm_errata_reproduced) { 2809 2810 unsigned long *page = alloc_pages(1); 2811 2812 if (!page) { 2813 report_pass("All guest memory tested, no bug found"); 2814 break; 2815 } 2816 2817 physical = virt_to_phys(page); 2818 2819 asm volatile ( 2820 "mov %[_physical], %%rax\n\t" 2821 "vmsave %%rax\n\t" 2822 2823 : [_physical] "=m" (physical) 2824 : /* no inputs*/ 2825 : "rax" /*clobbers*/ 2826 ); 2827 2828 if (svm_errata_reproduced) { 2829 report_fail("Got #GP exception - svm errata reproduced at 0x%lx", 2830 physical); 2831 break; 2832 } 2833 2834 *page = (unsigned long)last_page; 2835 last_page = page; 2836 } 2837 2838 while (last_page) { 2839 unsigned long *page = last_page; 2840 last_page = (unsigned long *)*last_page; 2841 free_pages_by_order(page, 1); 2842 } 2843 } 2844 2845 static void vmload_vmsave_guest_main(struct svm_test *test) 2846 { 2847 u64 vmcb_phys = virt_to_phys(vmcb); 2848 2849 asm volatile ("vmload %0" : : "a"(vmcb_phys)); 2850 asm volatile ("vmsave %0" : : "a"(vmcb_phys)); 2851 } 2852 2853 static void svm_vmload_vmsave(void) 2854 { 2855 u32 intercept_saved = vmcb->control.intercept; 2856 2857 test_set_guest(vmload_vmsave_guest_main); 2858 2859 /* 2860 * Disabling intercept for VMLOAD and VMSAVE doesn't cause 2861 * respective #VMEXIT to host 2862 */ 2863 vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMLOAD); 2864 vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMSAVE); 2865 svm_vmrun(); 2866 report(vmcb->control.exit_code == SVM_EXIT_VMMCALL, "Test " 2867 "VMLOAD/VMSAVE intercept: Expected VMMCALL #VMEXIT"); 2868 2869 /* 2870 * Enabling intercept for VMLOAD and VMSAVE causes respective 2871 * #VMEXIT to host 2872 */ 2873 vmcb->control.intercept |= (1ULL << INTERCEPT_VMLOAD); 2874 svm_vmrun(); 2875 report(vmcb->control.exit_code == SVM_EXIT_VMLOAD, "Test " 2876 "VMLOAD/VMSAVE intercept: Expected VMLOAD #VMEXIT"); 2877 vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMLOAD); 2878 vmcb->control.intercept |= (1ULL << INTERCEPT_VMSAVE); 2879 svm_vmrun(); 2880 report(vmcb->control.exit_code == SVM_EXIT_VMSAVE, "Test " 2881 "VMLOAD/VMSAVE intercept: Expected VMSAVE #VMEXIT"); 2882 vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMSAVE); 2883 svm_vmrun(); 2884 report(vmcb->control.exit_code == SVM_EXIT_VMMCALL, "Test " 2885 "VMLOAD/VMSAVE intercept: Expected VMMCALL #VMEXIT"); 2886 2887 vmcb->control.intercept |= (1ULL << INTERCEPT_VMLOAD); 2888 svm_vmrun(); 2889 report(vmcb->control.exit_code == SVM_EXIT_VMLOAD, "Test " 2890 "VMLOAD/VMSAVE intercept: Expected VMLOAD #VMEXIT"); 2891 vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMLOAD); 2892 svm_vmrun(); 2893 report(vmcb->control.exit_code == SVM_EXIT_VMMCALL, "Test " 2894 "VMLOAD/VMSAVE intercept: Expected VMMCALL #VMEXIT"); 2895 2896 vmcb->control.intercept |= (1ULL << INTERCEPT_VMSAVE); 2897 svm_vmrun(); 2898 report(vmcb->control.exit_code == SVM_EXIT_VMSAVE, "Test " 2899 "VMLOAD/VMSAVE intercept: Expected VMSAVE #VMEXIT"); 2900 vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMSAVE); 2901 svm_vmrun(); 2902 report(vmcb->control.exit_code == SVM_EXIT_VMMCALL, "Test " 2903 "VMLOAD/VMSAVE intercept: Expected VMMCALL #VMEXIT"); 2904 2905 vmcb->control.intercept = intercept_saved; 2906 } 2907 2908 static void prepare_vgif_enabled(struct svm_test *test) 2909 { 2910 default_prepare(test); 2911 } 2912 2913 static void test_vgif(struct svm_test *test) 2914 { 2915 asm volatile ("vmmcall\n\tstgi\n\tvmmcall\n\tclgi\n\tvmmcall\n\t"); 2916 2917 } 2918 2919 static bool vgif_finished(struct svm_test *test) 2920 { 2921 switch (get_test_stage(test)) 2922 { 2923 case 0: 2924 if (vmcb->control.exit_code != SVM_EXIT_VMMCALL) { 2925 report_fail("VMEXIT not due to vmmcall."); 2926 return true; 2927 } 2928 vmcb->control.int_ctl |= V_GIF_ENABLED_MASK; 2929 vmcb->save.rip += 3; 2930 inc_test_stage(test); 2931 break; 2932 case 1: 2933 if (vmcb->control.exit_code != SVM_EXIT_VMMCALL) { 2934 report_fail("VMEXIT not due to vmmcall."); 2935 return true; 2936 } 2937 if (!(vmcb->control.int_ctl & V_GIF_MASK)) { 2938 report_fail("Failed to set VGIF when executing STGI."); 2939 vmcb->control.int_ctl &= ~V_GIF_ENABLED_MASK; 2940 return true; 2941 } 2942 report_pass("STGI set VGIF bit."); 2943 vmcb->save.rip += 3; 2944 inc_test_stage(test); 2945 break; 2946 case 2: 2947 if (vmcb->control.exit_code != SVM_EXIT_VMMCALL) { 2948 report_fail("VMEXIT not due to vmmcall."); 2949 return true; 2950 } 2951 if (vmcb->control.int_ctl & V_GIF_MASK) { 2952 report_fail("Failed to clear VGIF when executing CLGI."); 2953 vmcb->control.int_ctl &= ~V_GIF_ENABLED_MASK; 2954 return true; 2955 } 2956 report_pass("CLGI cleared VGIF bit."); 2957 vmcb->save.rip += 3; 2958 inc_test_stage(test); 2959 vmcb->control.int_ctl &= ~V_GIF_ENABLED_MASK; 2960 break; 2961 default: 2962 return true; 2963 break; 2964 } 2965 2966 return get_test_stage(test) == 3; 2967 } 2968 2969 static bool vgif_check(struct svm_test *test) 2970 { 2971 return get_test_stage(test) == 3; 2972 } 2973 2974 2975 struct svm_test svm_tests[] = { 2976 { "null", default_supported, default_prepare, 2977 default_prepare_gif_clear, null_test, 2978 default_finished, null_check }, 2979 { "vmrun", default_supported, default_prepare, 2980 default_prepare_gif_clear, test_vmrun, 2981 default_finished, check_vmrun }, 2982 { "ioio", default_supported, prepare_ioio, 2983 default_prepare_gif_clear, test_ioio, 2984 ioio_finished, check_ioio }, 2985 { "vmrun intercept check", default_supported, prepare_no_vmrun_int, 2986 default_prepare_gif_clear, null_test, default_finished, 2987 check_no_vmrun_int }, 2988 { "rsm", default_supported, 2989 prepare_rsm_intercept, default_prepare_gif_clear, 2990 test_rsm_intercept, finished_rsm_intercept, check_rsm_intercept }, 2991 { "cr3 read intercept", default_supported, 2992 prepare_cr3_intercept, default_prepare_gif_clear, 2993 test_cr3_intercept, default_finished, check_cr3_intercept }, 2994 { "cr3 read nointercept", default_supported, default_prepare, 2995 default_prepare_gif_clear, test_cr3_intercept, default_finished, 2996 check_cr3_nointercept }, 2997 { "cr3 read intercept emulate", smp_supported, 2998 prepare_cr3_intercept_bypass, default_prepare_gif_clear, 2999 test_cr3_intercept_bypass, default_finished, check_cr3_intercept }, 3000 { "dr intercept check", default_supported, prepare_dr_intercept, 3001 default_prepare_gif_clear, test_dr_intercept, dr_intercept_finished, 3002 check_dr_intercept }, 3003 { "next_rip", next_rip_supported, prepare_next_rip, 3004 default_prepare_gif_clear, test_next_rip, 3005 default_finished, check_next_rip }, 3006 { "msr intercept check", default_supported, prepare_msr_intercept, 3007 default_prepare_gif_clear, test_msr_intercept, 3008 msr_intercept_finished, check_msr_intercept }, 3009 { "mode_switch", default_supported, prepare_mode_switch, 3010 default_prepare_gif_clear, test_mode_switch, 3011 mode_switch_finished, check_mode_switch }, 3012 { "asid_zero", default_supported, prepare_asid_zero, 3013 default_prepare_gif_clear, test_asid_zero, 3014 default_finished, check_asid_zero }, 3015 { "sel_cr0_bug", default_supported, sel_cr0_bug_prepare, 3016 default_prepare_gif_clear, sel_cr0_bug_test, 3017 sel_cr0_bug_finished, sel_cr0_bug_check }, 3018 { "npt_nx", npt_supported, npt_nx_prepare, 3019 default_prepare_gif_clear, null_test, 3020 default_finished, npt_nx_check }, 3021 { "npt_np", npt_supported, npt_np_prepare, 3022 default_prepare_gif_clear, npt_np_test, 3023 default_finished, npt_np_check }, 3024 { "npt_us", npt_supported, npt_us_prepare, 3025 default_prepare_gif_clear, npt_us_test, 3026 default_finished, npt_us_check }, 3027 { "npt_rw", npt_supported, npt_rw_prepare, 3028 default_prepare_gif_clear, npt_rw_test, 3029 default_finished, npt_rw_check }, 3030 { "npt_rw_pfwalk", npt_supported, npt_rw_pfwalk_prepare, 3031 default_prepare_gif_clear, null_test, 3032 default_finished, npt_rw_pfwalk_check }, 3033 { "npt_l1mmio", npt_supported, npt_l1mmio_prepare, 3034 default_prepare_gif_clear, npt_l1mmio_test, 3035 default_finished, npt_l1mmio_check }, 3036 { "npt_rw_l1mmio", npt_supported, npt_rw_l1mmio_prepare, 3037 default_prepare_gif_clear, npt_rw_l1mmio_test, 3038 default_finished, npt_rw_l1mmio_check }, 3039 { "tsc_adjust", tsc_adjust_supported, tsc_adjust_prepare, 3040 default_prepare_gif_clear, tsc_adjust_test, 3041 default_finished, tsc_adjust_check }, 3042 { "latency_run_exit", default_supported, latency_prepare, 3043 default_prepare_gif_clear, latency_test, 3044 latency_finished, latency_check }, 3045 { "latency_run_exit_clean", default_supported, latency_prepare, 3046 default_prepare_gif_clear, latency_test, 3047 latency_finished_clean, latency_check }, 3048 { "latency_svm_insn", default_supported, lat_svm_insn_prepare, 3049 default_prepare_gif_clear, null_test, 3050 lat_svm_insn_finished, lat_svm_insn_check }, 3051 { "exc_inject", default_supported, exc_inject_prepare, 3052 default_prepare_gif_clear, exc_inject_test, 3053 exc_inject_finished, exc_inject_check }, 3054 { "pending_event", default_supported, pending_event_prepare, 3055 default_prepare_gif_clear, 3056 pending_event_test, pending_event_finished, pending_event_check }, 3057 { "pending_event_cli", default_supported, pending_event_cli_prepare, 3058 pending_event_cli_prepare_gif_clear, 3059 pending_event_cli_test, pending_event_cli_finished, 3060 pending_event_cli_check }, 3061 { "interrupt", default_supported, interrupt_prepare, 3062 default_prepare_gif_clear, interrupt_test, 3063 interrupt_finished, interrupt_check }, 3064 { "nmi", default_supported, nmi_prepare, 3065 default_prepare_gif_clear, nmi_test, 3066 nmi_finished, nmi_check }, 3067 { "nmi_hlt", smp_supported, nmi_prepare, 3068 default_prepare_gif_clear, nmi_hlt_test, 3069 nmi_hlt_finished, nmi_hlt_check }, 3070 { "virq_inject", default_supported, virq_inject_prepare, 3071 default_prepare_gif_clear, virq_inject_test, 3072 virq_inject_finished, virq_inject_check }, 3073 { "reg_corruption", default_supported, reg_corruption_prepare, 3074 default_prepare_gif_clear, reg_corruption_test, 3075 reg_corruption_finished, reg_corruption_check }, 3076 { "svm_init_startup_test", smp_supported, init_startup_prepare, 3077 default_prepare_gif_clear, null_test, 3078 init_startup_finished, init_startup_check }, 3079 { "svm_init_intercept_test", smp_supported, init_intercept_prepare, 3080 default_prepare_gif_clear, init_intercept_test, 3081 init_intercept_finished, init_intercept_check, .on_vcpu = 2 }, 3082 { "host_rflags", default_supported, host_rflags_prepare, 3083 host_rflags_prepare_gif_clear, host_rflags_test, 3084 host_rflags_finished, host_rflags_check }, 3085 { "vgif", vgif_supported, prepare_vgif_enabled, 3086 default_prepare_gif_clear, test_vgif, vgif_finished, 3087 vgif_check }, 3088 TEST(svm_cr4_osxsave_test), 3089 TEST(svm_guest_state_test), 3090 TEST(svm_npt_rsvd_bits_test), 3091 TEST(svm_vmrun_errata_test), 3092 TEST(svm_vmload_vmsave), 3093 TEST(svm_test_singlestep), 3094 { NULL, NULL, NULL, NULL, NULL, NULL, NULL } 3095 }; 3096