1 #ifndef _X86_PROCESSOR_H_ 2 #define _X86_PROCESSOR_H_ 3 4 #include "libcflat.h" 5 #include "desc.h" 6 #include "msr.h" 7 #include <bitops.h> 8 #include <stdint.h> 9 10 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 11 12 #ifdef __x86_64__ 13 # define R "r" 14 # define W "q" 15 # define S "8" 16 #else 17 # define R "e" 18 # define W "l" 19 # define S "4" 20 #endif 21 22 #define DE_VECTOR 0 23 #define DB_VECTOR 1 24 #define NMI_VECTOR 2 25 #define BP_VECTOR 3 26 #define OF_VECTOR 4 27 #define BR_VECTOR 5 28 #define UD_VECTOR 6 29 #define NM_VECTOR 7 30 #define DF_VECTOR 8 31 #define TS_VECTOR 10 32 #define NP_VECTOR 11 33 #define SS_VECTOR 12 34 #define GP_VECTOR 13 35 #define PF_VECTOR 14 36 #define MF_VECTOR 16 37 #define AC_VECTOR 17 38 #define MC_VECTOR 18 39 #define XM_VECTOR 19 40 #define XF_VECTOR XM_VECTOR /* AMD */ 41 #define VE_VECTOR 20 /* Intel only */ 42 #define CP_VECTOR 21 43 #define HV_VECTOR 28 /* AMD only */ 44 #define VC_VECTOR 29 /* AMD only */ 45 #define SX_VECTOR 30 /* AMD only */ 46 47 #define X86_CR0_PE_BIT (0) 48 #define X86_CR0_PE BIT(X86_CR0_PE_BIT) 49 #define X86_CR0_MP_BIT (1) 50 #define X86_CR0_MP BIT(X86_CR0_MP_BIT) 51 #define X86_CR0_EM_BIT (2) 52 #define X86_CR0_EM BIT(X86_CR0_EM_BIT) 53 #define X86_CR0_TS_BIT (3) 54 #define X86_CR0_TS BIT(X86_CR0_TS_BIT) 55 #define X86_CR0_ET_BIT (4) 56 #define X86_CR0_ET BIT(X86_CR0_ET_BIT) 57 #define X86_CR0_NE_BIT (5) 58 #define X86_CR0_NE BIT(X86_CR0_NE_BIT) 59 #define X86_CR0_WP_BIT (16) 60 #define X86_CR0_WP BIT(X86_CR0_WP_BIT) 61 #define X86_CR0_AM_BIT (18) 62 #define X86_CR0_AM BIT(X86_CR0_AM_BIT) 63 #define X86_CR0_NW_BIT (29) 64 #define X86_CR0_NW BIT(X86_CR0_NW_BIT) 65 #define X86_CR0_CD_BIT (30) 66 #define X86_CR0_CD BIT(X86_CR0_CD_BIT) 67 #define X86_CR0_PG_BIT (31) 68 #define X86_CR0_PG BIT(X86_CR0_PG_BIT) 69 70 #define X86_CR3_PCID_MASK GENMASK(11, 0) 71 72 #define X86_CR4_VME_BIT (0) 73 #define X86_CR4_VME BIT(X86_CR4_VME_BIT) 74 #define X86_CR4_PVI_BIT (1) 75 #define X86_CR4_PVI BIT(X86_CR4_PVI_BIT) 76 #define X86_CR4_TSD_BIT (2) 77 #define X86_CR4_TSD BIT(X86_CR4_TSD_BIT) 78 #define X86_CR4_DE_BIT (3) 79 #define X86_CR4_DE BIT(X86_CR4_DE_BIT) 80 #define X86_CR4_PSE_BIT (4) 81 #define X86_CR4_PSE BIT(X86_CR4_PSE_BIT) 82 #define X86_CR4_PAE_BIT (5) 83 #define X86_CR4_PAE BIT(X86_CR4_PAE_BIT) 84 #define X86_CR4_MCE_BIT (6) 85 #define X86_CR4_MCE BIT(X86_CR4_MCE_BIT) 86 #define X86_CR4_PGE_BIT (7) 87 #define X86_CR4_PGE BIT(X86_CR4_PGE_BIT) 88 #define X86_CR4_PCE_BIT (8) 89 #define X86_CR4_PCE BIT(X86_CR4_PCE_BIT) 90 #define X86_CR4_OSFXSR_BIT (9) 91 #define X86_CR4_OSFXSR BIT(X86_CR4_OSFXSR_BIT) 92 #define X86_CR4_OSXMMEXCPT_BIT (10) 93 #define X86_CR4_OSXMMEXCPT BIT(X86_CR4_OSXMMEXCPT_BIT) 94 #define X86_CR4_UMIP_BIT (11) 95 #define X86_CR4_UMIP BIT(X86_CR4_UMIP_BIT) 96 #define X86_CR4_LA57_BIT (12) 97 #define X86_CR4_LA57 BIT(X86_CR4_LA57_BIT) 98 #define X86_CR4_VMXE_BIT (13) 99 #define X86_CR4_VMXE BIT(X86_CR4_VMXE_BIT) 100 #define X86_CR4_SMXE_BIT (14) 101 #define X86_CR4_SMXE BIT(X86_CR4_SMXE_BIT) 102 /* UNUSED (15) */ 103 #define X86_CR4_FSGSBASE_BIT (16) 104 #define X86_CR4_FSGSBASE BIT(X86_CR4_FSGSBASE_BIT) 105 #define X86_CR4_PCIDE_BIT (17) 106 #define X86_CR4_PCIDE BIT(X86_CR4_PCIDE_BIT) 107 #define X86_CR4_OSXSAVE_BIT (18) 108 #define X86_CR4_OSXSAVE BIT(X86_CR4_OSXSAVE_BIT) 109 #define X86_CR4_KL_BIT (19) 110 #define X86_CR4_KL BIT(X86_CR4_KL_BIT) 111 #define X86_CR4_SMEP_BIT (20) 112 #define X86_CR4_SMEP BIT(X86_CR4_SMEP_BIT) 113 #define X86_CR4_SMAP_BIT (21) 114 #define X86_CR4_SMAP BIT(X86_CR4_SMAP_BIT) 115 #define X86_CR4_PKE_BIT (22) 116 #define X86_CR4_PKE BIT(X86_CR4_PKE_BIT) 117 #define X86_CR4_CET_BIT (23) 118 #define X86_CR4_CET BIT(X86_CR4_CET_BIT) 119 #define X86_CR4_PKS_BIT (24) 120 #define X86_CR4_PKS BIT(X86_CR4_PKS_BIT) 121 122 #define X86_EFLAGS_CF_BIT (0) 123 #define X86_EFLAGS_CF BIT(X86_EFLAGS_CF_BIT) 124 #define X86_EFLAGS_FIXED_BIT (1) 125 #define X86_EFLAGS_FIXED BIT(X86_EFLAGS_FIXED_BIT) 126 #define X86_EFLAGS_PF_BIT (2) 127 #define X86_EFLAGS_PF BIT(X86_EFLAGS_PF_BIT) 128 /* RESERVED 0 (3) */ 129 #define X86_EFLAGS_AF_BIT (4) 130 #define X86_EFLAGS_AF BIT(X86_EFLAGS_AF_BIT) 131 /* RESERVED 0 (5) */ 132 #define X86_EFLAGS_ZF_BIT (6) 133 #define X86_EFLAGS_ZF BIT(X86_EFLAGS_ZF_BIT) 134 #define X86_EFLAGS_SF_BIT (7) 135 #define X86_EFLAGS_SF BIT(X86_EFLAGS_SF_BIT) 136 #define X86_EFLAGS_TF_BIT (8) 137 #define X86_EFLAGS_TF BIT(X86_EFLAGS_TF_BIT) 138 #define X86_EFLAGS_IF_BIT (9) 139 #define X86_EFLAGS_IF BIT(X86_EFLAGS_IF_BIT) 140 #define X86_EFLAGS_DF_BIT (10) 141 #define X86_EFLAGS_DF BIT(X86_EFLAGS_DF_BIT) 142 #define X86_EFLAGS_OF_BIT (11) 143 #define X86_EFLAGS_OF BIT(X86_EFLAGS_OF_BIT) 144 #define X86_EFLAGS_IOPL GENMASK(13, 12) 145 #define X86_EFLAGS_NT_BIT (14) 146 #define X86_EFLAGS_NT BIT(X86_EFLAGS_NT_BIT) 147 /* RESERVED 0 (15) */ 148 #define X86_EFLAGS_RF_BIT (16) 149 #define X86_EFLAGS_RF BIT(X86_EFLAGS_RF_BIT) 150 #define X86_EFLAGS_VM_BIT (17) 151 #define X86_EFLAGS_VM BIT(X86_EFLAGS_VM_BIT) 152 #define X86_EFLAGS_AC_BIT (18) 153 #define X86_EFLAGS_AC BIT(X86_EFLAGS_AC_BIT) 154 #define X86_EFLAGS_VIF_BIT (19) 155 #define X86_EFLAGS_VIF BIT(X86_EFLAGS_VIF_BIT) 156 #define X86_EFLAGS_VIP_BIT (20) 157 #define X86_EFLAGS_VIP BIT(X86_EFLAGS_VIP_BIT) 158 #define X86_EFLAGS_ID_BIT (21) 159 #define X86_EFLAGS_ID BIT(X86_EFLAGS_ID_BIT) 160 161 #define X86_EFLAGS_ALU (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | \ 162 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF) 163 164 165 /* 166 * CPU features 167 */ 168 169 enum cpuid_output_regs { 170 EAX, 171 EBX, 172 ECX, 173 EDX 174 }; 175 176 struct cpuid { u32 a, b, c, d; }; 177 178 static inline struct cpuid raw_cpuid(u32 function, u32 index) 179 { 180 struct cpuid r; 181 asm volatile ("cpuid" 182 : "=a"(r.a), "=b"(r.b), "=c"(r.c), "=d"(r.d) 183 : "0"(function), "2"(index)); 184 return r; 185 } 186 187 static inline struct cpuid cpuid_indexed(u32 function, u32 index) 188 { 189 u32 level = raw_cpuid(function & 0xf0000000, 0).a; 190 if (level < function) 191 return (struct cpuid) { 0, 0, 0, 0 }; 192 return raw_cpuid(function, index); 193 } 194 195 static inline struct cpuid cpuid(u32 function) 196 { 197 return cpuid_indexed(function, 0); 198 } 199 200 static inline u8 cpuid_maxphyaddr(void) 201 { 202 if (raw_cpuid(0x80000000, 0).a < 0x80000008) 203 return 36; 204 return raw_cpuid(0x80000008, 0).a & 0xff; 205 } 206 207 static inline bool is_intel(void) 208 { 209 struct cpuid c = cpuid(0); 210 u32 name[4] = {c.b, c.d, c.c }; 211 212 return strcmp((char *)name, "GenuineIntel") == 0; 213 } 214 215 #define CPUID(a, b, c, d) ((((unsigned long long) a) << 32) | (b << 16) | \ 216 (c << 8) | d) 217 218 /* 219 * Each X86_FEATURE_XXX definition is 64-bit and contains the following 220 * CPUID meta-data: 221 * 222 * [63:32] : input value for EAX 223 * [31:16] : input value for ECX 224 * [15:8] : output register 225 * [7:0] : bit position in output register 226 */ 227 228 /* 229 * Basic Leafs, a.k.a. Intel defined 230 */ 231 #define X86_FEATURE_MWAIT (CPUID(0x1, 0, ECX, 3)) 232 #define X86_FEATURE_VMX (CPUID(0x1, 0, ECX, 5)) 233 #define X86_FEATURE_PDCM (CPUID(0x1, 0, ECX, 15)) 234 #define X86_FEATURE_PCID (CPUID(0x1, 0, ECX, 17)) 235 #define X86_FEATURE_X2APIC (CPUID(0x1, 0, ECX, 21)) 236 #define X86_FEATURE_MOVBE (CPUID(0x1, 0, ECX, 22)) 237 #define X86_FEATURE_TSC_DEADLINE_TIMER (CPUID(0x1, 0, ECX, 24)) 238 #define X86_FEATURE_XSAVE (CPUID(0x1, 0, ECX, 26)) 239 #define X86_FEATURE_OSXSAVE (CPUID(0x1, 0, ECX, 27)) 240 #define X86_FEATURE_RDRAND (CPUID(0x1, 0, ECX, 30)) 241 #define X86_FEATURE_MCE (CPUID(0x1, 0, EDX, 7)) 242 #define X86_FEATURE_APIC (CPUID(0x1, 0, EDX, 9)) 243 #define X86_FEATURE_CLFLUSH (CPUID(0x1, 0, EDX, 19)) 244 #define X86_FEATURE_XMM (CPUID(0x1, 0, EDX, 25)) 245 #define X86_FEATURE_XMM2 (CPUID(0x1, 0, EDX, 26)) 246 #define X86_FEATURE_TSC_ADJUST (CPUID(0x7, 0, EBX, 1)) 247 #define X86_FEATURE_HLE (CPUID(0x7, 0, EBX, 4)) 248 #define X86_FEATURE_SMEP (CPUID(0x7, 0, EBX, 7)) 249 #define X86_FEATURE_INVPCID (CPUID(0x7, 0, EBX, 10)) 250 #define X86_FEATURE_RTM (CPUID(0x7, 0, EBX, 11)) 251 #define X86_FEATURE_SMAP (CPUID(0x7, 0, EBX, 20)) 252 #define X86_FEATURE_PCOMMIT (CPUID(0x7, 0, EBX, 22)) 253 #define X86_FEATURE_CLFLUSHOPT (CPUID(0x7, 0, EBX, 23)) 254 #define X86_FEATURE_CLWB (CPUID(0x7, 0, EBX, 24)) 255 #define X86_FEATURE_UMIP (CPUID(0x7, 0, ECX, 2)) 256 #define X86_FEATURE_PKU (CPUID(0x7, 0, ECX, 3)) 257 #define X86_FEATURE_LA57 (CPUID(0x7, 0, ECX, 16)) 258 #define X86_FEATURE_RDPID (CPUID(0x7, 0, ECX, 22)) 259 #define X86_FEATURE_SHSTK (CPUID(0x7, 0, ECX, 7)) 260 #define X86_FEATURE_IBT (CPUID(0x7, 0, EDX, 20)) 261 #define X86_FEATURE_SPEC_CTRL (CPUID(0x7, 0, EDX, 26)) 262 #define X86_FEATURE_FLUSH_L1D (CPUID(0x7, 0, EDX, 28)) 263 #define X86_FEATURE_ARCH_CAPABILITIES (CPUID(0x7, 0, EDX, 29)) 264 #define X86_FEATURE_PKS (CPUID(0x7, 0, ECX, 31)) 265 266 /* 267 * Extended Leafs, a.k.a. AMD defined 268 */ 269 #define X86_FEATURE_SVM (CPUID(0x80000001, 0, ECX, 2)) 270 #define X86_FEATURE_PERFCTR_CORE (CPUID(0x80000001, 0, ECX, 23)) 271 #define X86_FEATURE_NX (CPUID(0x80000001, 0, EDX, 20)) 272 #define X86_FEATURE_GBPAGES (CPUID(0x80000001, 0, EDX, 26)) 273 #define X86_FEATURE_RDTSCP (CPUID(0x80000001, 0, EDX, 27)) 274 #define X86_FEATURE_LM (CPUID(0x80000001, 0, EDX, 29)) 275 #define X86_FEATURE_RDPRU (CPUID(0x80000008, 0, EBX, 4)) 276 #define X86_FEATURE_AMD_IBPB (CPUID(0x80000008, 0, EBX, 12)) 277 #define X86_FEATURE_NPT (CPUID(0x8000000A, 0, EDX, 0)) 278 #define X86_FEATURE_LBRV (CPUID(0x8000000A, 0, EDX, 1)) 279 #define X86_FEATURE_NRIPS (CPUID(0x8000000A, 0, EDX, 3)) 280 #define X86_FEATURE_TSCRATEMSR (CPUID(0x8000000A, 0, EDX, 4)) 281 #define X86_FEATURE_PAUSEFILTER (CPUID(0x8000000A, 0, EDX, 10)) 282 #define X86_FEATURE_PFTHRESHOLD (CPUID(0x8000000A, 0, EDX, 12)) 283 #define X86_FEATURE_VGIF (CPUID(0x8000000A, 0, EDX, 16)) 284 #define X86_FEATURE_VNMI (CPUID(0x8000000A, 0, EDX, 25)) 285 #define X86_FEATURE_AMD_PMU_V2 (CPUID(0x80000022, 0, EAX, 0)) 286 287 static inline bool this_cpu_has(u64 feature) 288 { 289 u32 input_eax = feature >> 32; 290 u32 input_ecx = (feature >> 16) & 0xffff; 291 u32 output_reg = (feature >> 8) & 0xff; 292 u8 bit = feature & 0xff; 293 struct cpuid c; 294 u32 *tmp; 295 296 c = cpuid_indexed(input_eax, input_ecx); 297 tmp = (u32 *)&c; 298 299 return ((*(tmp + (output_reg % 32))) & (1 << bit)); 300 } 301 302 struct far_pointer32 { 303 u32 offset; 304 u16 selector; 305 } __attribute__((packed)); 306 307 struct descriptor_table_ptr { 308 u16 limit; 309 ulong base; 310 } __attribute__((packed)); 311 312 static inline void clac(void) 313 { 314 asm volatile (".byte 0x0f, 0x01, 0xca" : : : "memory"); 315 } 316 317 static inline void stac(void) 318 { 319 asm volatile (".byte 0x0f, 0x01, 0xcb" : : : "memory"); 320 } 321 322 static inline u16 read_cs(void) 323 { 324 unsigned val; 325 326 asm volatile ("mov %%cs, %0" : "=mr"(val)); 327 return val; 328 } 329 330 static inline u16 read_ds(void) 331 { 332 unsigned val; 333 334 asm volatile ("mov %%ds, %0" : "=mr"(val)); 335 return val; 336 } 337 338 static inline u16 read_es(void) 339 { 340 unsigned val; 341 342 asm volatile ("mov %%es, %0" : "=mr"(val)); 343 return val; 344 } 345 346 static inline u16 read_ss(void) 347 { 348 unsigned val; 349 350 asm volatile ("mov %%ss, %0" : "=mr"(val)); 351 return val; 352 } 353 354 static inline u16 read_fs(void) 355 { 356 unsigned val; 357 358 asm volatile ("mov %%fs, %0" : "=mr"(val)); 359 return val; 360 } 361 362 static inline u16 read_gs(void) 363 { 364 unsigned val; 365 366 asm volatile ("mov %%gs, %0" : "=mr"(val)); 367 return val; 368 } 369 370 static inline unsigned long read_rflags(void) 371 { 372 unsigned long f; 373 asm volatile ("pushf; pop %0\n\t" : "=rm"(f)); 374 return f; 375 } 376 377 static inline void write_ds(unsigned val) 378 { 379 asm volatile ("mov %0, %%ds" : : "rm"(val) : "memory"); 380 } 381 382 static inline void write_es(unsigned val) 383 { 384 asm volatile ("mov %0, %%es" : : "rm"(val) : "memory"); 385 } 386 387 static inline void write_ss(unsigned val) 388 { 389 asm volatile ("mov %0, %%ss" : : "rm"(val) : "memory"); 390 } 391 392 static inline void write_fs(unsigned val) 393 { 394 asm volatile ("mov %0, %%fs" : : "rm"(val) : "memory"); 395 } 396 397 static inline void write_gs(unsigned val) 398 { 399 asm volatile ("mov %0, %%gs" : : "rm"(val) : "memory"); 400 } 401 402 static inline void write_rflags(unsigned long f) 403 { 404 asm volatile ("push %0; popf\n\t" : : "rm"(f)); 405 } 406 407 static inline void set_iopl(int iopl) 408 { 409 unsigned long flags = read_rflags() & ~X86_EFLAGS_IOPL; 410 flags |= iopl * (X86_EFLAGS_IOPL / 3); 411 write_rflags(flags); 412 } 413 414 /* 415 * Don't use the safe variants for rdmsr() or wrmsr(). The exception fixup 416 * infrastructure uses per-CPU data and thus consumes GS.base. Various tests 417 * temporarily modify MSR_GS_BASE and will explode when trying to determine 418 * whether or not RDMSR/WRMSR faulted. 419 */ 420 static inline u64 rdmsr(u32 index) 421 { 422 u32 a, d; 423 asm volatile ("rdmsr" : "=a"(a), "=d"(d) : "c"(index) : "memory"); 424 return a | ((u64)d << 32); 425 } 426 427 static inline void wrmsr(u32 index, u64 val) 428 { 429 u32 a = val, d = val >> 32; 430 asm volatile ("wrmsr" : : "a"(a), "d"(d), "c"(index) : "memory"); 431 } 432 433 #define rdreg64_safe(insn, index, val) \ 434 ({ \ 435 uint32_t a, d; \ 436 int vector; \ 437 \ 438 vector = asm_safe_out2(insn, "=a"(a), "=d"(d), "c"(index)); \ 439 \ 440 if (vector) \ 441 *(val) = 0; \ 442 else \ 443 *(val) = (uint64_t)a | ((uint64_t)d << 32); \ 444 vector; \ 445 }) 446 447 #define wrreg64_safe(insn, index, val) \ 448 ({ \ 449 uint32_t eax = (val), edx = (val) >> 32; \ 450 \ 451 asm_safe(insn, "a" (eax), "d" (edx), "c" (index)); \ 452 }) 453 454 455 static inline int rdmsr_safe(u32 index, uint64_t *val) 456 { 457 return rdreg64_safe("rdmsr", index, val); 458 } 459 460 static inline int wrmsr_safe(u32 index, u64 val) 461 { 462 return wrreg64_safe("wrmsr", index, val); 463 } 464 465 static inline int rdpmc_safe(u32 index, uint64_t *val) 466 { 467 return rdreg64_safe("rdpmc", index, val); 468 } 469 470 static inline uint64_t rdpmc(uint32_t index) 471 { 472 uint64_t val; 473 int vector = rdpmc_safe(index, &val); 474 475 assert_msg(!vector, "Unexpected %s on RDPMC(%" PRId32 ")", 476 exception_mnemonic(vector), index); 477 return val; 478 } 479 480 static inline int xgetbv_safe(u32 index, u64 *result) 481 { 482 return rdreg64_safe(".byte 0x0f,0x01,0xd0", index, result); 483 } 484 485 static inline int xsetbv_safe(u32 index, u64 value) 486 { 487 return wrreg64_safe(".byte 0x0f,0x01,0xd1", index, value); 488 } 489 490 static inline int write_cr0_safe(ulong val) 491 { 492 return asm_safe("mov %0,%%cr0", "r" (val)); 493 } 494 495 static inline void write_cr0(ulong val) 496 { 497 int vector = write_cr0_safe(val); 498 499 assert_msg(!vector, "Unexpected fault '%d' writing CR0 = %lx", 500 vector, val); 501 } 502 503 static inline ulong read_cr0(void) 504 { 505 ulong val; 506 asm volatile ("mov %%cr0, %0" : "=r"(val) : : "memory"); 507 return val; 508 } 509 510 static inline void write_cr2(ulong val) 511 { 512 asm volatile ("mov %0, %%cr2" : : "r"(val) : "memory"); 513 } 514 515 static inline ulong read_cr2(void) 516 { 517 ulong val; 518 asm volatile ("mov %%cr2, %0" : "=r"(val) : : "memory"); 519 return val; 520 } 521 522 static inline int write_cr3_safe(ulong val) 523 { 524 return asm_safe("mov %0,%%cr3", "r" (val)); 525 } 526 527 static inline void write_cr3(ulong val) 528 { 529 int vector = write_cr3_safe(val); 530 531 assert_msg(!vector, "Unexpected fault '%d' writing CR3 = %lx", 532 vector, val); 533 } 534 535 static inline ulong read_cr3(void) 536 { 537 ulong val; 538 asm volatile ("mov %%cr3, %0" : "=r"(val) : : "memory"); 539 return val; 540 } 541 542 static inline void update_cr3(void *cr3) 543 { 544 write_cr3((ulong)cr3); 545 } 546 547 static inline int write_cr4_safe(ulong val) 548 { 549 return asm_safe("mov %0,%%cr4", "r" (val)); 550 } 551 552 static inline void write_cr4(ulong val) 553 { 554 int vector = write_cr4_safe(val); 555 556 assert_msg(!vector, "Unexpected fault '%d' writing CR4 = %lx", 557 vector, val); 558 } 559 560 static inline ulong read_cr4(void) 561 { 562 ulong val; 563 asm volatile ("mov %%cr4, %0" : "=r"(val) : : "memory"); 564 return val; 565 } 566 567 static inline void write_cr8(ulong val) 568 { 569 asm volatile ("mov %0, %%cr8" : : "r"(val) : "memory"); 570 } 571 572 static inline ulong read_cr8(void) 573 { 574 ulong val; 575 asm volatile ("mov %%cr8, %0" : "=r"(val) : : "memory"); 576 return val; 577 } 578 579 static inline void lgdt(const struct descriptor_table_ptr *ptr) 580 { 581 asm volatile ("lgdt %0" : : "m"(*ptr)); 582 } 583 584 static inline void sgdt(struct descriptor_table_ptr *ptr) 585 { 586 asm volatile ("sgdt %0" : "=m"(*ptr)); 587 } 588 589 static inline void lidt(const struct descriptor_table_ptr *ptr) 590 { 591 asm volatile ("lidt %0" : : "m"(*ptr)); 592 } 593 594 static inline void sidt(struct descriptor_table_ptr *ptr) 595 { 596 asm volatile ("sidt %0" : "=m"(*ptr)); 597 } 598 599 static inline void lldt(u16 val) 600 { 601 asm volatile ("lldt %0" : : "rm"(val)); 602 } 603 604 static inline u16 sldt(void) 605 { 606 u16 val; 607 asm volatile ("sldt %0" : "=rm"(val)); 608 return val; 609 } 610 611 static inline void ltr(u16 val) 612 { 613 asm volatile ("ltr %0" : : "rm"(val)); 614 } 615 616 static inline u16 str(void) 617 { 618 u16 val; 619 asm volatile ("str %0" : "=rm"(val)); 620 return val; 621 } 622 623 static inline void write_dr0(void *val) 624 { 625 asm volatile ("mov %0, %%dr0" : : "r"(val) : "memory"); 626 } 627 628 static inline void write_dr1(void *val) 629 { 630 asm volatile ("mov %0, %%dr1" : : "r"(val) : "memory"); 631 } 632 633 static inline void write_dr2(void *val) 634 { 635 asm volatile ("mov %0, %%dr2" : : "r"(val) : "memory"); 636 } 637 638 static inline void write_dr3(void *val) 639 { 640 asm volatile ("mov %0, %%dr3" : : "r"(val) : "memory"); 641 } 642 643 static inline void write_dr6(ulong val) 644 { 645 asm volatile ("mov %0, %%dr6" : : "r"(val) : "memory"); 646 } 647 648 static inline ulong read_dr6(void) 649 { 650 ulong val; 651 asm volatile ("mov %%dr6, %0" : "=r"(val)); 652 return val; 653 } 654 655 static inline void write_dr7(ulong val) 656 { 657 asm volatile ("mov %0, %%dr7" : : "r"(val) : "memory"); 658 } 659 660 static inline ulong read_dr7(void) 661 { 662 ulong val; 663 asm volatile ("mov %%dr7, %0" : "=r"(val)); 664 return val; 665 } 666 667 static inline void pause(void) 668 { 669 asm volatile ("pause"); 670 } 671 672 static inline void cli(void) 673 { 674 asm volatile ("cli"); 675 } 676 677 /* 678 * See also safe_halt(). 679 */ 680 static inline void sti(void) 681 { 682 asm volatile ("sti"); 683 } 684 685 /* 686 * Enable interrupts and ensure that interrupts are evaluated upon return from 687 * this function, i.e. execute a nop to consume the STi interrupt shadow. 688 */ 689 static inline void sti_nop(void) 690 { 691 asm volatile ("sti; nop"); 692 } 693 694 /* 695 * Enable interrupts for one instruction (nop), to allow the CPU to process all 696 * interrupts that are already pending. 697 */ 698 static inline void sti_nop_cli(void) 699 { 700 asm volatile ("sti; nop; cli"); 701 } 702 703 static inline unsigned long long rdrand(void) 704 { 705 long long r; 706 707 asm volatile("rdrand %0\n\t" 708 "jc 1f\n\t" 709 "mov $0, %0\n\t" 710 "1:\n\t" : "=r" (r)); 711 return r; 712 } 713 714 static inline unsigned long long rdtsc(void) 715 { 716 long long r; 717 718 #ifdef __x86_64__ 719 unsigned a, d; 720 721 asm volatile ("rdtsc" : "=a"(a), "=d"(d)); 722 r = a | ((long long)d << 32); 723 #else 724 asm volatile ("rdtsc" : "=A"(r)); 725 #endif 726 return r; 727 } 728 729 /* 730 * Per the advice in the SDM, volume 2, the sequence "mfence; lfence" 731 * executed immediately before rdtsc ensures that rdtsc will be 732 * executed only after all previous instructions have executed and all 733 * previous loads and stores are globally visible. In addition, the 734 * lfence immediately after rdtsc ensures that rdtsc will be executed 735 * prior to the execution of any subsequent instruction. 736 */ 737 static inline unsigned long long fenced_rdtsc(void) 738 { 739 unsigned long long tsc; 740 741 #ifdef __x86_64__ 742 unsigned int eax, edx; 743 744 asm volatile ("mfence; lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx)); 745 tsc = eax | ((unsigned long long)edx << 32); 746 #else 747 asm volatile ("mfence; lfence; rdtsc; lfence" : "=A"(tsc)); 748 #endif 749 return tsc; 750 } 751 752 static inline unsigned long long rdtscp(u32 *aux) 753 { 754 long long r; 755 756 #ifdef __x86_64__ 757 unsigned a, d; 758 759 asm volatile ("rdtscp" : "=a"(a), "=d"(d), "=c"(*aux)); 760 r = a | ((long long)d << 32); 761 #else 762 asm volatile ("rdtscp" : "=A"(r), "=c"(*aux)); 763 #endif 764 return r; 765 } 766 767 static inline void wrtsc(u64 tsc) 768 { 769 wrmsr(MSR_IA32_TSC, tsc); 770 } 771 772 773 static inline void invlpg(volatile void *va) 774 { 775 asm volatile("invlpg (%0)" ::"r" (va) : "memory"); 776 } 777 778 779 static inline int invpcid_safe(unsigned long type, void *desc) 780 { 781 /* invpcid (%rax), %rbx */ 782 return asm_safe(".byte 0x66,0x0f,0x38,0x82,0x18", "a" (desc), "b" (type)); 783 } 784 785 /* 786 * Execute HLT in an STI interrupt shadow to ensure that a pending IRQ that's 787 * intended to be a wake event arrives *after* HLT is executed. Modern CPUs, 788 * except for a few oddballs that KVM is unlikely to run on, block IRQs for one 789 * instruction after STI, *if* RFLAGS.IF=0 before STI. Note, Intel CPUs may 790 * block other events beyond regular IRQs, e.g. may block NMIs and SMIs too. 791 */ 792 static inline void safe_halt(void) 793 { 794 asm volatile("sti; hlt"); 795 } 796 797 static inline u32 read_pkru(void) 798 { 799 unsigned int eax, edx; 800 unsigned int ecx = 0; 801 unsigned int pkru; 802 803 asm volatile(".byte 0x0f,0x01,0xee\n\t" 804 : "=a" (eax), "=d" (edx) 805 : "c" (ecx)); 806 pkru = eax; 807 return pkru; 808 } 809 810 static inline void write_pkru(u32 pkru) 811 { 812 unsigned int eax = pkru; 813 unsigned int ecx = 0; 814 unsigned int edx = 0; 815 816 asm volatile(".byte 0x0f,0x01,0xef\n\t" 817 : : "a" (eax), "c" (ecx), "d" (edx)); 818 } 819 820 static inline bool is_canonical(u64 addr) 821 { 822 int va_width = (raw_cpuid(0x80000008, 0).a & 0xff00) >> 8; 823 int shift_amt = 64 - va_width; 824 825 return (s64)(addr << shift_amt) >> shift_amt == addr; 826 } 827 828 static inline void clear_bit(int bit, u8 *addr) 829 { 830 __asm__ __volatile__("btr %1, %0" 831 : "+m" (*addr) : "Ir" (bit) : "cc", "memory"); 832 } 833 834 static inline void set_bit(int bit, u8 *addr) 835 { 836 __asm__ __volatile__("bts %1, %0" 837 : "+m" (*addr) : "Ir" (bit) : "cc", "memory"); 838 } 839 840 static inline void flush_tlb(void) 841 { 842 ulong cr4; 843 844 cr4 = read_cr4(); 845 write_cr4(cr4 ^ X86_CR4_PGE); 846 write_cr4(cr4); 847 } 848 849 static inline void generate_non_canonical_gp(void) 850 { 851 *(volatile u64 *)NONCANONICAL = 0; 852 } 853 854 static inline void generate_ud(void) 855 { 856 asm volatile ("ud2"); 857 } 858 859 static inline void generate_de(void) 860 { 861 asm volatile ( 862 "xor %%eax, %%eax\n\t" 863 "xor %%ebx, %%ebx\n\t" 864 "xor %%edx, %%edx\n\t" 865 "idiv %%ebx\n\t" 866 ::: "eax", "ebx", "edx"); 867 } 868 869 static inline void generate_bp(void) 870 { 871 asm volatile ("int3"); 872 } 873 874 static inline void generate_single_step_db(void) 875 { 876 write_rflags(read_rflags() | X86_EFLAGS_TF); 877 asm volatile("nop"); 878 } 879 880 static inline uint64_t generate_usermode_ac(void) 881 { 882 /* 883 * Trigger an #AC by writing 8 bytes to a 4-byte aligned address. 884 * Disclaimer: It is assumed that the stack pointer is aligned 885 * on a 16-byte boundary as x86_64 stacks should be. 886 */ 887 asm volatile("movq $0, -0x4(%rsp)"); 888 889 return 0; 890 } 891 892 /* 893 * Switch from 64-bit to 32-bit mode and generate #OF via INTO. Note, if RIP 894 * or RSP holds a 64-bit value, this helper will NOT generate #OF. 895 */ 896 static inline void generate_of(void) 897 { 898 struct far_pointer32 fp = { 899 .offset = (uintptr_t)&&into, 900 .selector = KERNEL_CS32, 901 }; 902 uintptr_t rsp; 903 904 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 905 906 if (fp.offset != (uintptr_t)&&into) { 907 printf("Code address too high.\n"); 908 return; 909 } 910 if ((u32)rsp != rsp) { 911 printf("Stack address too high.\n"); 912 return; 913 } 914 915 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 916 return; 917 into: 918 asm volatile (".code32;" 919 "movl $0x7fffffff, %eax;" 920 "addl %eax, %eax;" 921 "into;" 922 "lret;" 923 ".code64"); 924 __builtin_unreachable(); 925 } 926 927 static inline void fnop(void) 928 { 929 asm volatile("fnop"); 930 } 931 932 /* If CR0.TS is set in L2, #NM is generated. */ 933 static inline void generate_cr0_ts_nm(void) 934 { 935 write_cr0((read_cr0() & ~X86_CR0_EM) | X86_CR0_TS); 936 fnop(); 937 } 938 939 /* If CR0.TS is cleared and CR0.EM is set, #NM is generated. */ 940 static inline void generate_cr0_em_nm(void) 941 { 942 write_cr0((read_cr0() & ~X86_CR0_TS) | X86_CR0_EM); 943 fnop(); 944 } 945 946 #endif 947