1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2017 Red Hat Inc 4 * 5 * Authors: 6 * David Hildenbrand <david@redhat.com> 7 */ 8 #ifndef _ASMS390X_ARCH_DEF_H_ 9 #define _ASMS390X_ARCH_DEF_H_ 10 11 struct stack_frame { 12 struct stack_frame *back_chain; 13 uint64_t reserved; 14 /* GRs 2 - 5 */ 15 uint64_t argument_area[4]; 16 /* GRs 6 - 15 */ 17 uint64_t grs[10]; 18 /* FPRs 0, 2, 4, 6 */ 19 int64_t fprs[4]; 20 }; 21 22 struct stack_frame_int { 23 struct stack_frame *back_chain; 24 uint64_t reserved; 25 /* 26 * The GRs are offset compatible with struct stack_frame so we 27 * can easily fetch GR14 for backtraces. 28 */ 29 /* GRs 2 - 15 */ 30 uint64_t grs0[14]; 31 /* GRs 0 and 1 */ 32 uint64_t grs1[2]; 33 uint32_t reserved1; 34 uint32_t fpc; 35 uint64_t fprs[16]; 36 uint64_t crs[16]; 37 }; 38 39 struct psw { 40 uint64_t mask; 41 uint64_t addr; 42 }; 43 44 #define PSW_MASK_EXT 0x0100000000000000UL 45 #define PSW_MASK_IO 0x0200000000000000UL 46 #define PSW_MASK_DAT 0x0400000000000000UL 47 #define PSW_MASK_WAIT 0x0002000000000000UL 48 #define PSW_MASK_PSTATE 0x0001000000000000UL 49 #define PSW_MASK_EA 0x0000000100000000UL 50 #define PSW_MASK_BA 0x0000000080000000UL 51 #define PSW_MASK_64 PSW_MASK_BA | PSW_MASK_EA; 52 53 #define CR0_EXTM_SCLP 0x0000000000000200UL 54 #define CR0_EXTM_EXTC 0x0000000000002000UL 55 #define CR0_EXTM_EMGC 0x0000000000004000UL 56 #define CR0_EXTM_MASK 0x0000000000006200UL 57 58 struct lowcore { 59 uint8_t pad_0x0000[0x0080 - 0x0000]; /* 0x0000 */ 60 uint32_t ext_int_param; /* 0x0080 */ 61 uint16_t cpu_addr; /* 0x0084 */ 62 uint16_t ext_int_code; /* 0x0086 */ 63 uint16_t svc_int_id; /* 0x0088 */ 64 uint16_t svc_int_code; /* 0x008a */ 65 uint16_t pgm_int_id; /* 0x008c */ 66 uint16_t pgm_int_code; /* 0x008e */ 67 uint32_t dxc_vxc; /* 0x0090 */ 68 uint16_t mon_class_nb; /* 0x0094 */ 69 uint8_t per_code; /* 0x0096 */ 70 uint8_t per_atmid; /* 0x0097 */ 71 uint64_t per_addr; /* 0x0098 */ 72 uint8_t exc_acc_id; /* 0x00a0 */ 73 uint8_t per_acc_id; /* 0x00a1 */ 74 uint8_t op_acc_id; /* 0x00a2 */ 75 uint8_t arch_mode_id; /* 0x00a3 */ 76 uint8_t pad_0x00a4[0x00a8 - 0x00a4]; /* 0x00a4 */ 77 uint64_t trans_exc_id; /* 0x00a8 */ 78 uint64_t mon_code; /* 0x00b0 */ 79 uint32_t subsys_id_word; /* 0x00b8 */ 80 uint32_t io_int_param; /* 0x00bc */ 81 uint32_t io_int_word; /* 0x00c0 */ 82 uint8_t pad_0x00c4[0x00c8 - 0x00c4]; /* 0x00c4 */ 83 uint32_t stfl; /* 0x00c8 */ 84 uint8_t pad_0x00cc[0x00e8 - 0x00cc]; /* 0x00cc */ 85 uint64_t mcck_int_code; /* 0x00e8 */ 86 uint8_t pad_0x00f0[0x00f4 - 0x00f0]; /* 0x00f0 */ 87 uint32_t ext_damage_code; /* 0x00f4 */ 88 uint64_t failing_storage_addr; /* 0x00f8 */ 89 uint64_t emon_ca_origin; /* 0x0100 */ 90 uint32_t emon_ca_size; /* 0x0108 */ 91 uint32_t emon_exc_count; /* 0x010c */ 92 uint64_t breaking_event_addr; /* 0x0110 */ 93 uint8_t pad_0x0118[0x0120 - 0x0118]; /* 0x0118 */ 94 struct psw restart_old_psw; /* 0x0120 */ 95 struct psw ext_old_psw; /* 0x0130 */ 96 struct psw svc_old_psw; /* 0x0140 */ 97 struct psw pgm_old_psw; /* 0x0150 */ 98 struct psw mcck_old_psw; /* 0x0160 */ 99 struct psw io_old_psw; /* 0x0170 */ 100 uint8_t pad_0x0180[0x01a0 - 0x0180]; /* 0x0180 */ 101 struct psw restart_new_psw; /* 0x01a0 */ 102 struct psw ext_new_psw; /* 0x01b0 */ 103 struct psw svc_new_psw; /* 0x01c0 */ 104 struct psw pgm_new_psw; /* 0x01d0 */ 105 struct psw mcck_new_psw; /* 0x01e0 */ 106 struct psw io_new_psw; /* 0x01f0 */ 107 /* sw definition: save area for registers in interrupt handlers */ 108 uint64_t sw_int_grs[16]; /* 0x0200 */ 109 uint8_t pad_0x0280[0x0308 - 0x0280]; /* 0x0280 */ 110 uint64_t sw_int_crs[16]; /* 0x0308 */ 111 struct psw sw_int_psw; /* 0x0388 */ 112 uint8_t pad_0x0310[0x11b0 - 0x0398]; /* 0x0398 */ 113 uint64_t mcck_ext_sa_addr; /* 0x11b0 */ 114 uint8_t pad_0x11b8[0x1200 - 0x11b8]; /* 0x11b8 */ 115 uint64_t fprs_sa[16]; /* 0x1200 */ 116 uint64_t grs_sa[16]; /* 0x1280 */ 117 struct psw psw_sa; /* 0x1300 */ 118 uint8_t pad_0x1310[0x1318 - 0x1310]; /* 0x1310 */ 119 uint32_t prefix_sa; /* 0x1318 */ 120 uint32_t fpc_sa; /* 0x131c */ 121 uint8_t pad_0x1320[0x1324 - 0x1320]; /* 0x1320 */ 122 uint32_t tod_pr_sa; /* 0x1324 */ 123 uint64_t cputm_sa; /* 0x1328 */ 124 uint64_t cc_sa; /* 0x1330 */ 125 uint8_t pad_0x1338[0x1340 - 0x1338]; /* 0x1338 */ 126 uint32_t ars_sa[16]; /* 0x1340 */ 127 uint64_t crs_sa[16]; /* 0x1380 */ 128 uint8_t pad_0x1400[0x1800 - 0x1400]; /* 0x1400 */ 129 uint8_t pgm_int_tdb[0x1900 - 0x1800]; /* 0x1800 */ 130 } __attribute__ ((__packed__)); 131 _Static_assert(sizeof(struct lowcore) == 0x1900, "Lowcore size"); 132 133 #define PGM_INT_CODE_OPERATION 0x01 134 #define PGM_INT_CODE_PRIVILEGED_OPERATION 0x02 135 #define PGM_INT_CODE_EXECUTE 0x03 136 #define PGM_INT_CODE_PROTECTION 0x04 137 #define PGM_INT_CODE_ADDRESSING 0x05 138 #define PGM_INT_CODE_SPECIFICATION 0x06 139 #define PGM_INT_CODE_DATA 0x07 140 #define PGM_INT_CODE_FIXED_POINT_OVERFLOW 0x08 141 #define PGM_INT_CODE_FIXED_POINT_DIVIDE 0x09 142 #define PGM_INT_CODE_DECIMAL_OVERFLOW 0x0a 143 #define PGM_INT_CODE_DECIMAL_DIVIDE 0x0b 144 #define PGM_INT_CODE_HFP_EXPONENT_OVERFLOW 0x0c 145 #define PGM_INT_CODE_HFP_EXPONENT_UNDERFLOW 0x0d 146 #define PGM_INT_CODE_HFP_SIGNIFICANCE 0x0e 147 #define PGM_INT_CODE_HFP_DIVIDE 0x0f 148 #define PGM_INT_CODE_SEGMENT_TRANSLATION 0x10 149 #define PGM_INT_CODE_PAGE_TRANSLATION 0x11 150 #define PGM_INT_CODE_TRANSLATION_SPEC 0x12 151 #define PGM_INT_CODE_SPECIAL_OPERATION 0x13 152 #define PGM_INT_CODE_OPERAND 0x15 153 #define PGM_INT_CODE_TRACE_TABLE 0x16 154 #define PGM_INT_CODE_VECTOR_PROCESSING 0x1b 155 #define PGM_INT_CODE_SPACE_SWITCH_EVENT 0x1c 156 #define PGM_INT_CODE_HFP_SQUARE_ROOT 0x1d 157 #define PGM_INT_CODE_PC_TRANSLATION_SPEC 0x1f 158 #define PGM_INT_CODE_AFX_TRANSLATION 0x20 159 #define PGM_INT_CODE_ASX_TRANSLATION 0x21 160 #define PGM_INT_CODE_LX_TRANSLATION 0x22 161 #define PGM_INT_CODE_EX_TRANSLATION 0x23 162 #define PGM_INT_CODE_PRIMARY_AUTHORITY 0x24 163 #define PGM_INT_CODE_SECONDARY_AUTHORITY 0x25 164 #define PGM_INT_CODE_LFX_TRANSLATION 0x26 165 #define PGM_INT_CODE_LSX_TRANSLATION 0x27 166 #define PGM_INT_CODE_ALET_SPECIFICATION 0x28 167 #define PGM_INT_CODE_ALEN_TRANSLATION 0x29 168 #define PGM_INT_CODE_ALE_SEQUENCE 0x2a 169 #define PGM_INT_CODE_ASTE_VALIDITY 0x2b 170 #define PGM_INT_CODE_ASTE_SEQUENCE 0x2c 171 #define PGM_INT_CODE_EXTENDED_AUTHORITY 0x2d 172 #define PGM_INT_CODE_LSTE_SEQUENCE 0x2e 173 #define PGM_INT_CODE_ASTE_INSTANCE 0x2f 174 #define PGM_INT_CODE_STACK_FULL 0x30 175 #define PGM_INT_CODE_STACK_EMPTY 0x31 176 #define PGM_INT_CODE_STACK_SPECIFICATION 0x32 177 #define PGM_INT_CODE_STACK_TYPE 0x33 178 #define PGM_INT_CODE_STACK_OPERATION 0x34 179 #define PGM_INT_CODE_ASCE_TYPE 0x38 180 #define PGM_INT_CODE_REGION_FIRST_TRANS 0x39 181 #define PGM_INT_CODE_REGION_SECOND_TRANS 0x3a 182 #define PGM_INT_CODE_REGION_THIRD_TRANS 0x3b 183 #define PGM_INT_CODE_SECURE_STOR_ACCESS 0x3d 184 #define PGM_INT_CODE_NON_SECURE_STOR_ACCESS 0x3e 185 #define PGM_INT_CODE_SECURE_STOR_VIOLATION 0x3f 186 #define PGM_INT_CODE_MONITOR_EVENT 0x40 187 #define PGM_INT_CODE_PER 0x80 188 #define PGM_INT_CODE_CRYPTO_OPERATION 0x119 189 #define PGM_INT_CODE_TX_ABORTED_EVENT 0x200 190 191 struct cpuid { 192 uint64_t version : 8; 193 uint64_t id : 24; 194 uint64_t type : 16; 195 uint64_t format : 1; 196 uint64_t reserved : 15; 197 }; 198 199 #define SVC_LEAVE_PSTATE 1 200 201 static inline unsigned short stap(void) 202 { 203 unsigned short cpu_address; 204 205 asm volatile("stap %0" : "=Q" (cpu_address)); 206 return cpu_address; 207 } 208 209 static inline int tprot(unsigned long addr) 210 { 211 int cc; 212 213 asm volatile( 214 " tprot 0(%1),0\n" 215 " ipm %0\n" 216 " srl %0,28\n" 217 : "=d" (cc) : "a" (addr) : "cc"); 218 return cc; 219 } 220 221 static inline void lctlg(int cr, uint64_t value) 222 { 223 asm volatile( 224 " lctlg %1,%1,%0\n" 225 : : "Q" (value), "i" (cr)); 226 } 227 228 static inline uint64_t stctg(int cr) 229 { 230 uint64_t value; 231 232 asm volatile( 233 " stctg %1,%1,%0\n" 234 : "=Q" (value) : "i" (cr) : "memory"); 235 return value; 236 } 237 238 #define CTL0_LOW_ADDR_PROT (63 - 35) 239 #define CTL0_EDAT (63 - 40) 240 #define CTL0_IEP (63 - 43) 241 #define CTL0_AFP (63 - 45) 242 #define CTL0_VECTOR (63 - 46) 243 #define CTL0_EMERGENCY_SIGNAL (63 - 49) 244 #define CTL0_EXTERNAL_CALL (63 - 50) 245 #define CTL0_CLOCK_COMPARATOR (63 - 52) 246 #define CTL0_SERVICE_SIGNAL (63 - 54) 247 248 #define CTL2_GUARDED_STORAGE (63 - 59) 249 250 static inline void ctl_set_bit(int cr, unsigned int bit) 251 { 252 uint64_t reg; 253 254 reg = stctg(cr); 255 reg |= 1UL << bit; 256 lctlg(cr, reg); 257 } 258 259 static inline void ctl_clear_bit(int cr, unsigned int bit) 260 { 261 uint64_t reg; 262 263 reg = stctg(cr); 264 reg &= ~(1UL << bit); 265 lctlg(cr, reg); 266 } 267 268 static inline uint64_t extract_psw_mask(void) 269 { 270 uint32_t mask_upper = 0, mask_lower = 0; 271 272 asm volatile( 273 " epsw %0,%1\n" 274 : "=r" (mask_upper), "=a" (mask_lower)); 275 276 return (uint64_t) mask_upper << 32 | mask_lower; 277 } 278 279 static inline void load_psw_mask(uint64_t mask) 280 { 281 struct psw psw = { 282 .mask = mask, 283 .addr = 0, 284 }; 285 uint64_t tmp = 0; 286 287 asm volatile( 288 " larl %0,0f\n" 289 " stg %0,8(%1)\n" 290 " lpswe 0(%1)\n" 291 "0:\n" 292 : "+r" (tmp) : "a" (&psw) : "memory", "cc" ); 293 } 294 295 static inline void wait_for_interrupt(uint64_t irq_mask) 296 { 297 uint64_t psw_mask = extract_psw_mask(); 298 299 load_psw_mask(psw_mask | irq_mask | PSW_MASK_WAIT); 300 /* 301 * After being woken and having processed the interrupt, let's restore 302 * the PSW mask. 303 */ 304 load_psw_mask(psw_mask); 305 } 306 307 static inline void enter_pstate(void) 308 { 309 uint64_t mask; 310 311 mask = extract_psw_mask(); 312 mask |= PSW_MASK_PSTATE; 313 load_psw_mask(mask); 314 } 315 316 static inline void leave_pstate(void) 317 { 318 asm volatile(" svc %0\n" : : "i" (SVC_LEAVE_PSTATE)); 319 } 320 321 static inline int stsi(void *addr, int fc, int sel1, int sel2) 322 { 323 register int r0 asm("0") = (fc << 28) | sel1; 324 register int r1 asm("1") = sel2; 325 int cc; 326 327 asm volatile( 328 "stsi 0(%3)\n" 329 "ipm %[cc]\n" 330 "srl %[cc],28\n" 331 : "+d" (r0), [cc] "=d" (cc) 332 : "d" (r1), "a" (addr) 333 : "cc", "memory"); 334 return cc; 335 } 336 337 static inline unsigned long stsi_get_fc(void) 338 { 339 register unsigned long r0 asm("0") = 0; 340 register unsigned long r1 asm("1") = 0; 341 int cc; 342 343 asm volatile("stsi 0\n" 344 "ipm %[cc]\n" 345 "srl %[cc],28\n" 346 : "+d" (r0), [cc] "=d" (cc) 347 : "d" (r1) 348 : "cc", "memory"); 349 assert(!cc); 350 return r0 >> 28; 351 } 352 353 static inline int servc(uint32_t command, unsigned long sccb) 354 { 355 int cc; 356 357 asm volatile( 358 " .insn rre,0xb2200000,%1,%2\n" /* servc %1,%2 */ 359 " ipm %0\n" 360 " srl %0,28" 361 : "=&d" (cc) : "d" (command), "a" (sccb) 362 : "cc", "memory"); 363 return cc; 364 } 365 366 static inline void set_prefix(uint32_t new_prefix) 367 { 368 asm volatile(" spx %0" : : "Q" (new_prefix) : "memory"); 369 } 370 371 static inline uint32_t get_prefix(void) 372 { 373 uint32_t current_prefix; 374 375 asm volatile(" stpx %0" : "=Q" (current_prefix)); 376 return current_prefix; 377 } 378 379 #endif 380