1 /* 2 * Ripped off from arch/arm64/include/asm/sysreg.h 3 * 4 * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com> 5 * 6 * This work is licensed under the terms of the GNU LGPL, version 2. 7 */ 8 #ifndef _ASMARM64_SYSREG_H_ 9 #define _ASMARM64_SYSREG_H_ 10 11 #include <linux/const.h> 12 13 #define sys_reg(op0, op1, crn, crm, op2) \ 14 ((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5)) 15 16 #ifdef __ASSEMBLY__ 17 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 18 .equ .L__reg_num_x\num, \num 19 .endr 20 .equ .L__reg_num_xzr, 31 21 22 .macro mrs_s, rt, sreg 23 .inst 0xd5200000|(\sreg)|(.L__reg_num_\rt) 24 .endm 25 26 .macro msr_s, sreg, rt 27 .inst 0xd5000000|(\sreg)|(.L__reg_num_\rt) 28 .endm 29 #else 30 #include <libcflat.h> 31 32 #define read_sysreg(r) ({ \ 33 u64 __val; \ 34 asm volatile("mrs %0, " xstr(r) : "=r" (__val)); \ 35 __val; \ 36 }) 37 38 #define write_sysreg(v, r) do { \ 39 u64 __val = (u64)v; \ 40 asm volatile("msr " xstr(r) ", %x0" : : "rZ" (__val)); \ 41 } while (0) 42 43 #define read_sysreg_s(r) ({ \ 44 u64 __val; \ 45 asm volatile("mrs_s %0, " xstr(r) : "=r" (__val)); \ 46 __val; \ 47 }) 48 49 #define write_sysreg_s(v, r) do { \ 50 u64 __val = (u64)v; \ 51 asm volatile("msr_s " xstr(r) ", %x0" : : "rZ" (__val));\ 52 } while (0) 53 54 #define write_regn_el0(__reg, __n, __val) \ 55 write_sysreg((__val), __reg ## __n ## _el0) 56 57 #define read_regn_el0(__reg, __n) \ 58 read_sysreg(__reg ## __n ## _el0) 59 60 asm( 61 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" 62 " .equ .L__reg_num_x\\num, \\num\n" 63 " .endr\n" 64 " .equ .L__reg_num_xzr, 31\n" 65 "\n" 66 " .macro mrs_s, rt, sreg\n" 67 " .inst 0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n" 68 " .endm\n" 69 "\n" 70 " .macro msr_s, sreg, rt\n" 71 " .inst 0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n" 72 " .endm\n" 73 ); 74 #endif /* __ASSEMBLY__ */ 75 76 #define ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 77 #define ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) 78 #define ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) 79 #define ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) 80 #define ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) 81 82 /* System Control Register (SCTLR_EL1) bits */ 83 #define SCTLR_EL1_EE _BITULL(25) 84 #define SCTLR_EL1_WXN _BITULL(19) 85 #define SCTLR_EL1_I _BITULL(12) 86 #define SCTLR_EL1_SA0 _BITULL(4) 87 #define SCTLR_EL1_SA _BITULL(3) 88 #define SCTLR_EL1_C _BITULL(2) 89 #define SCTLR_EL1_A _BITULL(1) 90 #define SCTLR_EL1_M _BITULL(0) 91 92 #define SCTLR_EL1_RES1 (_BITULL(7) | _BITULL(8) | _BITULL(11) | _BITULL(20) | \ 93 _BITULL(22) | _BITULL(23) | _BITULL(28) | _BITULL(29)) 94 #define INIT_SCTLR_EL1_MMU_OFF \ 95 SCTLR_EL1_RES1 96 97 #endif /* _ASMARM64_SYSREG_H_ */ 98