1/* 2 * Boot entry point and assembler functions for aarch64 tests. 3 * 4 * Copyright (C) 2017, Red Hat Inc, Andrew Jones <drjones@redhat.com> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2. 7 */ 8#define __ASSEMBLY__ 9#include <auxinfo.h> 10#include <asm/asm-offsets.h> 11#include <asm/assembler.h> 12#include <asm/ptrace.h> 13#include <asm/page.h> 14#include <asm/pgtable-hwdef.h> 15#include <asm/thread_info.h> 16#include <asm/sysreg.h> 17 18.macro zero_range, tmp1, tmp2 199998: cmp \tmp1, \tmp2 20 b.eq 9997f 21 stp xzr, xzr, [\tmp1], #16 22 b 9998b 239997: 24.endm 25 26.section .init 27 28/* 29 * Bootloader params are in x0-x3. See kernel doc 30 * Documentation/arm64/booting.txt 31 */ 32.globl start 33start: 34 /* get our base address */ 35 adrp x4, start 36 add x4, x4, :lo12:start 37 38 /* 39 * Update all R_AARCH64_RELATIVE relocations using the table 40 * of Elf64_Rela entries between reloc_start/end. The build 41 * will not emit other relocation types. 42 * 43 * struct Elf64_Rela { 44 * uint64_t r_offset; 45 * uint64_t r_info; 46 * int64_t r_addend; 47 * } 48 */ 49 adrp x5, reloc_start 50 add x5, x5, :lo12:reloc_start 51 adrp x6, reloc_end 52 add x6, x6, :lo12:reloc_end 531: 54 cmp x5, x6 55 b.hs 1f 56 ldr x7, [x5] // r_offset 57 ldr x8, [x5, #16] // r_addend 58 add x8, x8, x4 // val = base + r_addend 59 str x8, [x4, x7] // base[r_offset] = val 60 add x5, x5, #24 61 b 1b 62 631: 64 /* zero BSS */ 65 adrp x4, bss 66 add x4, x4, :lo12:bss 67 adrp x5, ebss 68 add x5, x5, :lo12:ebss 69 zero_range x4, x5 70 71 /* zero and set up stack */ 72 adrp x5, stacktop 73 add x5, x5, :lo12:stacktop 74 sub x4, x5, #THREAD_SIZE 75 zero_range x4, x5 76 77 /* set SCTLR_EL1 to a known value */ 78 ldr x4, =INIT_SCTLR_EL1_MMU_OFF 79 msr sctlr_el1, x4 80 isb 81 82 mov x4, #1 83 msr spsel, x4 84 adrp x4, stackptr 85 add sp, x4, :lo12:stackptr 86 87 /* enable FP/ASIMD */ 88 mov x4, #(3 << 20) 89 msr cpacr_el1, x4 90 91 /* set up exception handling */ 92 bl exceptions_init 93 94 /* complete setup */ 95 bl setup // x0 is the addr of the dtb 96 bl get_mmu_off 97 cbnz x0, 1f 98 bl setup_vm 99 1001: 101 /* run the test */ 102 adrp x0, __argc 103 ldr x0, [x0, :lo12:__argc] 104 adrp x1, __argv 105 add x1, x1, :lo12:__argv 106 adrp x2, __environ 107 add x2, x2, :lo12:__environ 108 bl main 109 bl exit 110 b halt 111 112exceptions_init: 113 adrp x4, vector_table 114 add x4, x4, :lo12:vector_table 115 msr vbar_el1, x4 116 isb 117 ret 118 119.text 120 121.globl get_mmu_off 122get_mmu_off: 123 adrp x0, auxinfo 124 ldr x0, [x0, :lo12:auxinfo + 8] 125 and x0, x0, #AUXINFO_MMU_OFF 126 ret 127 128.globl secondary_entry 129secondary_entry: 130 /* Enable FP/ASIMD */ 131 mov x0, #(3 << 20) 132 msr cpacr_el1, x0 133 134 /* set up exception handling */ 135 bl exceptions_init 136 137 /* enable the MMU unless requested off */ 138 bl get_mmu_off 139 cbnz x0, 1f 140 adrp x0, mmu_idmap 141 ldr x0, [x0, :lo12:mmu_idmap] 142 bl asm_mmu_enable 143 1441: 145 /* set the stack */ 146 adrp x0, secondary_data 147 ldr x0, [x0, :lo12:secondary_data] 148 mov sp, x0 149 150 /* finish init in C code */ 151 bl secondary_cinit 152 153 /* x0 is now the entry function, run it */ 154 blr x0 155 b do_idle 156 157.globl halt 158halt: 1591: wfi 160 b 1b 161 162/* 163 * asm_mmu_enable 164 * Inputs: 165 * x0 is the base address of the translation table 166 * Outputs: none 167 * 168 * Adapted from 169 * arch/arm64/kernel/head.S 170 * arch/arm64/mm/proc.S 171 */ 172 173/* 174 * Memory region attributes for LPAE: 175 * 176 * n = AttrIndx[2:0] 177 * n MAIR 178 * DEVICE_nGnRnE 000 00000000 179 * DEVICE_nGnRE 001 00000100 180 * DEVICE_GRE 010 00001100 181 * NORMAL_NC 011 01000100 182 * NORMAL 100 11111111 183 * NORMAL_WT 101 10111011 184 * DEVICE_nGRE 110 00001000 185 */ 186#define MAIR(attr, mt) ((attr) << ((mt) * 8)) 187 188#if PAGE_SIZE == SZ_64K 189#define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K 190#elif PAGE_SIZE == SZ_16K 191#define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K 192#elif PAGE_SIZE == SZ_4K 193#define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K 194#endif 195 196.globl asm_mmu_enable 197asm_mmu_enable: 198 tlbi vmalle1 // invalidate I + D TLBs 199 dsb nsh 200 201 /* TCR */ 202 ldr x1, =TCR_TxSZ(VA_BITS) | \ 203 TCR_TG_FLAGS | \ 204 TCR_IRGN_WBWA | TCR_ORGN_WBWA | \ 205 TCR_SHARED 206 mrs x2, id_aa64mmfr0_el1 207 bfi x1, x2, #32, #3 208 msr tcr_el1, x1 209 210 /* MAIR */ 211 ldr x1, =MAIR(0x00, MT_DEVICE_nGnRnE) | \ 212 MAIR(0x04, MT_DEVICE_nGnRE) | \ 213 MAIR(0x0c, MT_DEVICE_GRE) | \ 214 MAIR(0x44, MT_NORMAL_NC) | \ 215 MAIR(0xff, MT_NORMAL) | \ 216 MAIR(0xbb, MT_NORMAL_WT) | \ 217 MAIR(0x08, MT_DEVICE_nGRE) 218 msr mair_el1, x1 219 220 /* TTBR0 */ 221 msr ttbr0_el1, x0 222 isb 223 224 /* SCTLR */ 225 mrs x1, sctlr_el1 226 orr x1, x1, SCTLR_EL1_C 227 orr x1, x1, SCTLR_EL1_I 228 orr x1, x1, SCTLR_EL1_M 229 msr sctlr_el1, x1 230 isb 231 232 ret 233 234.globl asm_mmu_disable 235asm_mmu_disable: 236 mrs x0, sctlr_el1 237 bic x0, x0, SCTLR_EL1_M 238 msr sctlr_el1, x0 239 isb 240 241 /* Clean + invalidate the entire memory */ 242 adrp x0, __phys_offset 243 ldr x0, [x0, :lo12:__phys_offset] 244 adrp x1, __phys_end 245 ldr x1, [x1, :lo12:__phys_end] 246 sub x1, x1, x0 247 dcache_by_line_op civac, sy, x0, x1, x2, x3 248 249 ret 250 251/* 252 * Vectors 253 * Adapted from arch/arm64/kernel/entry.S 254 */ 255.macro vector_stub, name, vec 256\name: 257 stp x0, x1, [sp, #-S_FRAME_SIZE]! 258 stp x2, x3, [sp, #16] 259 stp x4, x5, [sp, #32] 260 stp x6, x7, [sp, #48] 261 stp x8, x9, [sp, #64] 262 stp x10, x11, [sp, #80] 263 stp x12, x13, [sp, #96] 264 stp x14, x15, [sp, #112] 265 stp x16, x17, [sp, #128] 266 stp x18, x19, [sp, #144] 267 stp x20, x21, [sp, #160] 268 stp x22, x23, [sp, #176] 269 stp x24, x25, [sp, #192] 270 stp x26, x27, [sp, #208] 271 stp x28, x29, [sp, #224] 272 273 str x30, [sp, #S_LR] 274 275 .if \vec >= 8 276 mrs x1, sp_el0 277 .else 278 add x1, sp, #S_FRAME_SIZE 279 .endif 280 str x1, [sp, #S_SP] 281 282 mrs x1, elr_el1 283 mrs x2, spsr_el1 284 stp x1, x2, [sp, #S_PC] 285 286 mov x0, \vec 287 mov x1, sp 288 mrs x2, esr_el1 289 bl do_handle_exception 290 291 ldp x1, x2, [sp, #S_PC] 292 msr spsr_el1, x2 293 msr elr_el1, x1 294 295 .if \vec >= 8 296 ldr x1, [sp, #S_SP] 297 msr sp_el0, x1 298 .endif 299 300 ldr x30, [sp, #S_LR] 301 302 ldp x28, x29, [sp, #224] 303 ldp x26, x27, [sp, #208] 304 ldp x24, x25, [sp, #192] 305 ldp x22, x23, [sp, #176] 306 ldp x20, x21, [sp, #160] 307 ldp x18, x19, [sp, #144] 308 ldp x16, x17, [sp, #128] 309 ldp x14, x15, [sp, #112] 310 ldp x12, x13, [sp, #96] 311 ldp x10, x11, [sp, #80] 312 ldp x8, x9, [sp, #64] 313 ldp x6, x7, [sp, #48] 314 ldp x4, x5, [sp, #32] 315 ldp x2, x3, [sp, #16] 316 ldp x0, x1, [sp], #S_FRAME_SIZE 317 318 eret 319.endm 320 321vector_stub el1t_sync, 0 322vector_stub el1t_irq, 1 323vector_stub el1t_fiq, 2 324vector_stub el1t_error, 3 325 326vector_stub el1h_sync, 4 327vector_stub el1h_irq, 5 328vector_stub el1h_fiq, 6 329vector_stub el1h_error, 7 330 331vector_stub el0_sync_64, 8 332vector_stub el0_irq_64, 9 333vector_stub el0_fiq_64, 10 334vector_stub el0_error_64, 11 335 336vector_stub el0_sync_32, 12 337vector_stub el0_irq_32, 13 338vector_stub el0_fiq_32, 14 339vector_stub el0_error_32, 15 340 341.section .text.ex 342 343.macro ventry, label 344.align 7 345 b \label 346.endm 347 348.align 11 349vector_table: 350 ventry el1t_sync // Synchronous EL1t 351 ventry el1t_irq // IRQ EL1t 352 ventry el1t_fiq // FIQ EL1t 353 ventry el1t_error // Error EL1t 354 355 ventry el1h_sync // Synchronous EL1h 356 ventry el1h_irq // IRQ EL1h 357 ventry el1h_fiq // FIQ EL1h 358 ventry el1h_error // Error EL1h 359 360 ventry el0_sync_64 // Synchronous 64-bit EL0 361 ventry el0_irq_64 // IRQ 64-bit EL0 362 ventry el0_fiq_64 // FIQ 64-bit EL0 363 ventry el0_error_64 // Error 64-bit EL0 364 365 ventry el0_sync_32 // Synchronous 32-bit EL0 366 ventry el0_irq_32 // IRQ 32-bit EL0 367 ventry el0_fiq_32 // FIQ 32-bit EL0 368 ventry el0_error_32 // Error 32-bit EL0 369