1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2017 Red Hat Inc 4 * 5 * Authors: 6 * David Hildenbrand <david@redhat.com> 7 */ 8 #ifndef _ASMS390X_ARCH_DEF_H_ 9 #define _ASMS390X_ARCH_DEF_H_ 10 11 struct stack_frame { 12 struct stack_frame *back_chain; 13 uint64_t reserved; 14 /* GRs 2 - 5 */ 15 uint64_t argument_area[4]; 16 /* GRs 6 - 15 */ 17 uint64_t grs[10]; 18 /* FPRs 0, 2, 4, 6 */ 19 int64_t fprs[4]; 20 }; 21 22 struct stack_frame_int { 23 struct stack_frame *back_chain; 24 uint64_t reserved; 25 /* 26 * The GRs are offset compatible with struct stack_frame so we 27 * can easily fetch GR14 for backtraces. 28 */ 29 /* GRs 2 - 15 */ 30 uint64_t grs0[14]; 31 /* GRs 0 and 1 */ 32 uint64_t grs1[2]; 33 uint32_t reserved1; 34 uint32_t fpc; 35 uint64_t fprs[16]; 36 uint64_t crs[16]; 37 }; 38 39 struct psw { 40 uint64_t mask; 41 uint64_t addr; 42 }; 43 44 #define AS_PRIM 0 45 #define AS_ACCR 1 46 #define AS_SECN 2 47 #define AS_HOME 3 48 49 #define PSW_MASK_EXT 0x0100000000000000UL 50 #define PSW_MASK_IO 0x0200000000000000UL 51 #define PSW_MASK_DAT 0x0400000000000000UL 52 #define PSW_MASK_WAIT 0x0002000000000000UL 53 #define PSW_MASK_PSTATE 0x0001000000000000UL 54 #define PSW_MASK_EA 0x0000000100000000UL 55 #define PSW_MASK_BA 0x0000000080000000UL 56 #define PSW_MASK_64 (PSW_MASK_BA | PSW_MASK_EA) 57 58 #define CTL0_LOW_ADDR_PROT (63 - 35) 59 #define CTL0_EDAT (63 - 40) 60 #define CTL0_IEP (63 - 43) 61 #define CTL0_AFP (63 - 45) 62 #define CTL0_VECTOR (63 - 46) 63 #define CTL0_EMERGENCY_SIGNAL (63 - 49) 64 #define CTL0_EXTERNAL_CALL (63 - 50) 65 #define CTL0_CLOCK_COMPARATOR (63 - 52) 66 #define CTL0_SERVICE_SIGNAL (63 - 54) 67 #define CR0_EXTM_MASK 0x0000000000006200UL /* Combined external masks */ 68 69 #define CTL2_GUARDED_STORAGE (63 - 59) 70 71 struct lowcore { 72 uint8_t pad_0x0000[0x0080 - 0x0000]; /* 0x0000 */ 73 uint32_t ext_int_param; /* 0x0080 */ 74 uint16_t cpu_addr; /* 0x0084 */ 75 uint16_t ext_int_code; /* 0x0086 */ 76 uint16_t svc_int_id; /* 0x0088 */ 77 uint16_t svc_int_code; /* 0x008a */ 78 uint16_t pgm_int_id; /* 0x008c */ 79 uint16_t pgm_int_code; /* 0x008e */ 80 uint32_t dxc_vxc; /* 0x0090 */ 81 uint16_t mon_class_nb; /* 0x0094 */ 82 uint8_t per_code; /* 0x0096 */ 83 uint8_t per_atmid; /* 0x0097 */ 84 uint64_t per_addr; /* 0x0098 */ 85 uint8_t exc_acc_id; /* 0x00a0 */ 86 uint8_t per_acc_id; /* 0x00a1 */ 87 uint8_t op_acc_id; /* 0x00a2 */ 88 uint8_t arch_mode_id; /* 0x00a3 */ 89 uint8_t pad_0x00a4[0x00a8 - 0x00a4]; /* 0x00a4 */ 90 uint64_t trans_exc_id; /* 0x00a8 */ 91 uint64_t mon_code; /* 0x00b0 */ 92 uint32_t subsys_id_word; /* 0x00b8 */ 93 uint32_t io_int_param; /* 0x00bc */ 94 uint32_t io_int_word; /* 0x00c0 */ 95 uint8_t pad_0x00c4[0x00c8 - 0x00c4]; /* 0x00c4 */ 96 uint32_t stfl; /* 0x00c8 */ 97 uint8_t pad_0x00cc[0x00e8 - 0x00cc]; /* 0x00cc */ 98 uint64_t mcck_int_code; /* 0x00e8 */ 99 uint8_t pad_0x00f0[0x00f4 - 0x00f0]; /* 0x00f0 */ 100 uint32_t ext_damage_code; /* 0x00f4 */ 101 uint64_t failing_storage_addr; /* 0x00f8 */ 102 uint64_t emon_ca_origin; /* 0x0100 */ 103 uint32_t emon_ca_size; /* 0x0108 */ 104 uint32_t emon_exc_count; /* 0x010c */ 105 uint64_t breaking_event_addr; /* 0x0110 */ 106 uint8_t pad_0x0118[0x0120 - 0x0118]; /* 0x0118 */ 107 struct psw restart_old_psw; /* 0x0120 */ 108 struct psw ext_old_psw; /* 0x0130 */ 109 struct psw svc_old_psw; /* 0x0140 */ 110 struct psw pgm_old_psw; /* 0x0150 */ 111 struct psw mcck_old_psw; /* 0x0160 */ 112 struct psw io_old_psw; /* 0x0170 */ 113 uint8_t pad_0x0180[0x01a0 - 0x0180]; /* 0x0180 */ 114 struct psw restart_new_psw; /* 0x01a0 */ 115 struct psw ext_new_psw; /* 0x01b0 */ 116 struct psw svc_new_psw; /* 0x01c0 */ 117 struct psw pgm_new_psw; /* 0x01d0 */ 118 struct psw mcck_new_psw; /* 0x01e0 */ 119 struct psw io_new_psw; /* 0x01f0 */ 120 /* sw definition: save area for registers in interrupt handlers */ 121 uint64_t sw_int_grs[16]; /* 0x0200 */ 122 uint8_t pad_0x0280[0x0308 - 0x0280]; /* 0x0280 */ 123 uint64_t sw_int_crs[16]; /* 0x0308 */ 124 struct psw sw_int_psw; /* 0x0388 */ 125 uint8_t pad_0x0310[0x11b0 - 0x0398]; /* 0x0398 */ 126 uint64_t mcck_ext_sa_addr; /* 0x11b0 */ 127 uint8_t pad_0x11b8[0x1200 - 0x11b8]; /* 0x11b8 */ 128 uint64_t fprs_sa[16]; /* 0x1200 */ 129 uint64_t grs_sa[16]; /* 0x1280 */ 130 struct psw psw_sa; /* 0x1300 */ 131 uint8_t pad_0x1310[0x1318 - 0x1310]; /* 0x1310 */ 132 uint32_t prefix_sa; /* 0x1318 */ 133 uint32_t fpc_sa; /* 0x131c */ 134 uint8_t pad_0x1320[0x1324 - 0x1320]; /* 0x1320 */ 135 uint32_t tod_pr_sa; /* 0x1324 */ 136 uint64_t cputm_sa; /* 0x1328 */ 137 uint64_t cc_sa; /* 0x1330 */ 138 uint8_t pad_0x1338[0x1340 - 0x1338]; /* 0x1338 */ 139 uint32_t ars_sa[16]; /* 0x1340 */ 140 uint64_t crs_sa[16]; /* 0x1380 */ 141 uint8_t pad_0x1400[0x1800 - 0x1400]; /* 0x1400 */ 142 uint8_t pgm_int_tdb[0x1900 - 0x1800]; /* 0x1800 */ 143 } __attribute__ ((__packed__)); 144 _Static_assert(sizeof(struct lowcore) == 0x1900, "Lowcore size"); 145 146 #define PGM_INT_CODE_OPERATION 0x01 147 #define PGM_INT_CODE_PRIVILEGED_OPERATION 0x02 148 #define PGM_INT_CODE_EXECUTE 0x03 149 #define PGM_INT_CODE_PROTECTION 0x04 150 #define PGM_INT_CODE_ADDRESSING 0x05 151 #define PGM_INT_CODE_SPECIFICATION 0x06 152 #define PGM_INT_CODE_DATA 0x07 153 #define PGM_INT_CODE_FIXED_POINT_OVERFLOW 0x08 154 #define PGM_INT_CODE_FIXED_POINT_DIVIDE 0x09 155 #define PGM_INT_CODE_DECIMAL_OVERFLOW 0x0a 156 #define PGM_INT_CODE_DECIMAL_DIVIDE 0x0b 157 #define PGM_INT_CODE_HFP_EXPONENT_OVERFLOW 0x0c 158 #define PGM_INT_CODE_HFP_EXPONENT_UNDERFLOW 0x0d 159 #define PGM_INT_CODE_HFP_SIGNIFICANCE 0x0e 160 #define PGM_INT_CODE_HFP_DIVIDE 0x0f 161 #define PGM_INT_CODE_SEGMENT_TRANSLATION 0x10 162 #define PGM_INT_CODE_PAGE_TRANSLATION 0x11 163 #define PGM_INT_CODE_TRANSLATION_SPEC 0x12 164 #define PGM_INT_CODE_SPECIAL_OPERATION 0x13 165 #define PGM_INT_CODE_OPERAND 0x15 166 #define PGM_INT_CODE_TRACE_TABLE 0x16 167 #define PGM_INT_CODE_VECTOR_PROCESSING 0x1b 168 #define PGM_INT_CODE_SPACE_SWITCH_EVENT 0x1c 169 #define PGM_INT_CODE_HFP_SQUARE_ROOT 0x1d 170 #define PGM_INT_CODE_PC_TRANSLATION_SPEC 0x1f 171 #define PGM_INT_CODE_AFX_TRANSLATION 0x20 172 #define PGM_INT_CODE_ASX_TRANSLATION 0x21 173 #define PGM_INT_CODE_LX_TRANSLATION 0x22 174 #define PGM_INT_CODE_EX_TRANSLATION 0x23 175 #define PGM_INT_CODE_PRIMARY_AUTHORITY 0x24 176 #define PGM_INT_CODE_SECONDARY_AUTHORITY 0x25 177 #define PGM_INT_CODE_LFX_TRANSLATION 0x26 178 #define PGM_INT_CODE_LSX_TRANSLATION 0x27 179 #define PGM_INT_CODE_ALET_SPECIFICATION 0x28 180 #define PGM_INT_CODE_ALEN_TRANSLATION 0x29 181 #define PGM_INT_CODE_ALE_SEQUENCE 0x2a 182 #define PGM_INT_CODE_ASTE_VALIDITY 0x2b 183 #define PGM_INT_CODE_ASTE_SEQUENCE 0x2c 184 #define PGM_INT_CODE_EXTENDED_AUTHORITY 0x2d 185 #define PGM_INT_CODE_LSTE_SEQUENCE 0x2e 186 #define PGM_INT_CODE_ASTE_INSTANCE 0x2f 187 #define PGM_INT_CODE_STACK_FULL 0x30 188 #define PGM_INT_CODE_STACK_EMPTY 0x31 189 #define PGM_INT_CODE_STACK_SPECIFICATION 0x32 190 #define PGM_INT_CODE_STACK_TYPE 0x33 191 #define PGM_INT_CODE_STACK_OPERATION 0x34 192 #define PGM_INT_CODE_ASCE_TYPE 0x38 193 #define PGM_INT_CODE_REGION_FIRST_TRANS 0x39 194 #define PGM_INT_CODE_REGION_SECOND_TRANS 0x3a 195 #define PGM_INT_CODE_REGION_THIRD_TRANS 0x3b 196 #define PGM_INT_CODE_SECURE_STOR_ACCESS 0x3d 197 #define PGM_INT_CODE_NON_SECURE_STOR_ACCESS 0x3e 198 #define PGM_INT_CODE_SECURE_STOR_VIOLATION 0x3f 199 #define PGM_INT_CODE_MONITOR_EVENT 0x40 200 #define PGM_INT_CODE_PER 0x80 201 #define PGM_INT_CODE_CRYPTO_OPERATION 0x119 202 #define PGM_INT_CODE_TX_ABORTED_EVENT 0x200 203 204 struct cpuid { 205 uint64_t version : 8; 206 uint64_t id : 24; 207 uint64_t type : 16; 208 uint64_t format : 1; 209 uint64_t reserved : 15; 210 }; 211 212 #define SVC_LEAVE_PSTATE 1 213 214 static inline unsigned short stap(void) 215 { 216 unsigned short cpu_address; 217 218 asm volatile("stap %0" : "=Q" (cpu_address)); 219 return cpu_address; 220 } 221 222 #define MACHINE_Z15A 0x8561 223 #define MACHINE_Z15B 0x8562 224 225 static inline uint16_t get_machine_id(void) 226 { 227 uint64_t cpuid; 228 229 asm volatile("stidp %0" : "=Q" (cpuid)); 230 cpuid = cpuid >> 16; 231 cpuid &= 0xffff; 232 233 return cpuid; 234 } 235 236 static inline int tprot(unsigned long addr, char access_key) 237 { 238 int cc; 239 240 asm volatile( 241 " tprot 0(%1),0(%2)\n" 242 " ipm %0\n" 243 " srl %0,28\n" 244 : "=d" (cc) : "a" (addr), "a" (access_key << 4) : "cc"); 245 return cc; 246 } 247 248 static inline void lctlg(int cr, uint64_t value) 249 { 250 asm volatile( 251 " lctlg %1,%1,%0\n" 252 : : "Q" (value), "i" (cr)); 253 } 254 255 static inline uint64_t stctg(int cr) 256 { 257 uint64_t value; 258 259 asm volatile( 260 " stctg %1,%1,%0\n" 261 : "=Q" (value) : "i" (cr) : "memory"); 262 return value; 263 } 264 265 static inline void ctl_set_bit(int cr, unsigned int bit) 266 { 267 uint64_t reg; 268 269 reg = stctg(cr); 270 reg |= 1UL << bit; 271 lctlg(cr, reg); 272 } 273 274 static inline void ctl_clear_bit(int cr, unsigned int bit) 275 { 276 uint64_t reg; 277 278 reg = stctg(cr); 279 reg &= ~(1UL << bit); 280 lctlg(cr, reg); 281 } 282 283 static inline uint64_t extract_psw_mask(void) 284 { 285 uint32_t mask_upper = 0, mask_lower = 0; 286 287 asm volatile( 288 " epsw %0,%1\n" 289 : "=r" (mask_upper), "=a" (mask_lower)); 290 291 return (uint64_t) mask_upper << 32 | mask_lower; 292 } 293 294 static inline void load_psw_mask(uint64_t mask) 295 { 296 struct psw psw = { 297 .mask = mask, 298 .addr = 0, 299 }; 300 uint64_t tmp = 0; 301 302 asm volatile( 303 " larl %0,0f\n" 304 " stg %0,8(%1)\n" 305 " lpswe 0(%1)\n" 306 "0:\n" 307 : "+r" (tmp) : "a" (&psw) : "memory", "cc" ); 308 } 309 310 static inline void wait_for_interrupt(uint64_t irq_mask) 311 { 312 uint64_t psw_mask = extract_psw_mask(); 313 314 load_psw_mask(psw_mask | irq_mask | PSW_MASK_WAIT); 315 /* 316 * After being woken and having processed the interrupt, let's restore 317 * the PSW mask. 318 */ 319 load_psw_mask(psw_mask); 320 } 321 322 static inline void enter_pstate(void) 323 { 324 uint64_t mask; 325 326 mask = extract_psw_mask(); 327 mask |= PSW_MASK_PSTATE; 328 load_psw_mask(mask); 329 } 330 331 static inline void leave_pstate(void) 332 { 333 asm volatile(" svc %0\n" : : "i" (SVC_LEAVE_PSTATE)); 334 } 335 336 static inline int stsi(void *addr, int fc, int sel1, int sel2) 337 { 338 register int r0 asm("0") = (fc << 28) | sel1; 339 register int r1 asm("1") = sel2; 340 int cc; 341 342 asm volatile( 343 "stsi 0(%3)\n" 344 "ipm %[cc]\n" 345 "srl %[cc],28\n" 346 : "+d" (r0), [cc] "=d" (cc) 347 : "d" (r1), "a" (addr) 348 : "cc", "memory"); 349 return cc; 350 } 351 352 static inline unsigned long stsi_get_fc(void) 353 { 354 register unsigned long r0 asm("0") = 0; 355 register unsigned long r1 asm("1") = 0; 356 int cc; 357 358 asm volatile("stsi 0\n" 359 "ipm %[cc]\n" 360 "srl %[cc],28\n" 361 : "+d" (r0), [cc] "=d" (cc) 362 : "d" (r1) 363 : "cc", "memory"); 364 assert(!cc); 365 return r0 >> 28; 366 } 367 368 static inline int servc(uint32_t command, unsigned long sccb) 369 { 370 int cc; 371 372 asm volatile( 373 " .insn rre,0xb2200000,%1,%2\n" /* servc %1,%2 */ 374 " ipm %0\n" 375 " srl %0,28" 376 : "=&d" (cc) : "d" (command), "a" (sccb) 377 : "cc", "memory"); 378 return cc; 379 } 380 381 static inline void set_prefix(uint32_t new_prefix) 382 { 383 asm volatile(" spx %0" : : "Q" (new_prefix) : "memory"); 384 } 385 386 static inline uint32_t get_prefix(void) 387 { 388 uint32_t current_prefix; 389 390 asm volatile(" stpx %0" : "=Q" (current_prefix)); 391 return current_prefix; 392 } 393 394 #endif 395