| /linux-3.3/Documentation/cgroups/ |
| D | memory.txt | 1 Memory Resource Controller
3 NOTE: The Memory Resource Controller has generically been referred to as the
4 memory controller in this document. Do not confuse memory controller
5 used here with the memory controller that is used in hardware.
9 When we mention a cgroup (cgroupfs's directory) with memory controller,
10 we call it "memory cgroup". When you see git-log and source code, you'll
14 Benefits and Purpose of the memory controller
16 The memory controller isolates the memory behaviour of a group of tasks
18 uses of the memory controller. The memory controller can be used to
21 Memory hungry applications can be isolated and limited to a smaller
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| D | 00-INDEX | 1 00-INDEX
2 - this file
4 - Control Groups definition, implementation details, examples and API.
6 - CPU Accounting Controller; account CPU usage for groups of tasks.
8 - documents the cpusets feature; assign CPUs and Mem to a set of tasks.
10 - Device Whitelist Controller; description, interface and security.
11 freezer-subsystem.txt
12 - checkpointing; rationale to not use signals, interface.
14 - Memory Resource Controller; implementation details.
15 memory.txt
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| /linux-3.3/drivers/char/agp/ |
| D | frontend.c | 4 * Copyright (C) 2002-2003 Dave Jones
55 curr = agp_fe.current_controller->pool; in agp_find_mem_by_key()
58 if (curr->key == key) in agp_find_mem_by_key()
60 curr = curr->next; in agp_find_mem_by_key()
63 DBG("key=%d -> mem=%p", key, curr); in agp_find_mem_by_key()
72 /* Check to see if this is even in the memory pool */ in agp_remove_from_pool()
75 if (agp_find_mem_by_key(temp->key) != NULL) { in agp_remove_from_pool()
76 next = temp->next; in agp_remove_from_pool()
77 prev = temp->prev; in agp_remove_from_pool()
80 prev->next = next; in agp_remove_from_pool()
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| /linux-3.3/drivers/edac/ |
| D | ppc4xx_edac.c | 29 * associated with the IMB DDR2 ECC controller found in the AMCC/IBM
32 * As realized in the 405EX[r], this controller features:
34 * - Support for registered- and non-registered DDR1 and DDR2 memory.
35 * - 32-bit or 16-bit memory interface with optional ECC.
39 * - 4-bit SEC/DED
40 * - Aligned-nibble error detect
41 * - Bypass mode
43 * - Two (2) memory banks/ranks.
44 * - Up to 1 GiB per bank/rank in 32-bit mode and up to 512 MiB per
45 * bank/rank in 16-bit mode.
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| D | Kconfig | 13 These are low-level errors that are reported in the CPU or
15 memory errors, cache errors, PCI errors, thermal throttling, etc..
38 sub-system. You can insert module with "debug_level=x", current
43 tristate "Decode MCEs in human-readable form (only on AMD for now)"
46 ---help---
48 occurring on your machine in human-readable form.
62 This is currently AMD-only.
65 tristate "Main Memory EDAC (Error Detection And Correction) reporting"
68 memory. EDAC can report statistics on memory error
69 detection and correction (EDAC - or commonly referred to ECC
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| D | mpc85xx_edac.c | 2 * Freescale MPC85xx Memory Controller kenel module
6 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
55 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; in mpc85xx_mc_inject_data_hi_show()
57 in_be32(pdata->mc_vbase + in mpc85xx_mc_inject_data_hi_show()
64 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; in mpc85xx_mc_inject_data_lo_show()
66 in_be32(pdata->mc_vbase + in mpc85xx_mc_inject_data_lo_show()
72 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; in mpc85xx_mc_inject_ctrl_show()
74 in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT)); in mpc85xx_mc_inject_ctrl_show()
80 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; in mpc85xx_mc_inject_data_hi_store()
82 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI, in mpc85xx_mc_inject_data_hi_store()
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| D | amd76x_edac.c | 2 * AMD 76x Memory Controller kernel module
9 * http://www.anime.net/~goemon/linux-ecc/
35 /* AMD 76x register addresses - device 0 function 0 - PCI bridge */
51 * 31:26 clock disable 5 - 0
59 * 17:16 cycles-per-refresh
61 * 7:0 x4 mode enable 7 - 0
64 #define AMD76X_MEM_BASE_ADDR 0xC0 /* Memory base address (8 x 32b)
66 * 31:23 chip-select base
68 * 15:7 chip-select mask
71 * 0 chip-select enable
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| /linux-3.3/arch/blackfin/mach-bf548/include/mach/ |
| D | defBF54x_base.h | 2 * Copyright 2007-2010 Analog Devices Inc.
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
12 /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
23 /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
31 /* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
102 …rs are not defined in the shared file because they are not available on the ADSP-BF542 processor */
124 /* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-…
151 /* Asynchronous Memory Control Registers */
153 #define EBIU_AMGCTL 0xffc00a00 /* Asynchronous Memory Global Control Regist…
154 #define EBIU_AMBCTL0 0xffc00a04 /* Asynchronous Memory Bank Control Register…
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| /linux-3.3/drivers/video/omap/ |
| D | Kconfig | 13 bool "External LCD controller support"
17 external LCD controller connected to the SoSSI/RFBI interface.
20 bool "Epson HWA742 LCD controller support"
24 Epson HWA742 LCD controller.
27 bool "Epson Blizzard LCD controller support"
31 Epson Blizzard LCD controller.
37 Say Y here, if your user-space applications are capable of
43 bool "MIPI DBI-C/DCS compatible LCD support"
47 the Mobile Industry Processor Interface DBI-C/DCS
55 already initialized the display controller. In this case the
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| /linux-3.3/Documentation/devicetree/bindings/dma/ |
| D | arm-pl330.txt | 1 * ARM PrimeCell PL330 DMA Controller
3 The ARM PrimeCell PL330 DMA controller can move blocks of memory contents
4 between memory and peripherals or memory to memory.
7 - compatible: should include both "arm,pl330" and "arm,primecell".
8 - reg: physical base address of the controller and length of memory mapped
10 - interrupts: interrupt number to the cpu.
20 Client drivers (device nodes requiring dma transfers from dev-to-mem or
21 mem-to-dev) should specify the DMA channel numbers using a two-value pair
24 [property name] = <[phandle of the dma controller] [dma request id]>;
27 to the client controller. The 'property name' is recommended to be
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| /linux-3.3/drivers/message/i2o/ |
| D | pci.c | 2 * PCI handling of I2O controller
4 * Copyright (C) 1999-2002 Red Hat Software
37 #define OSM_DESCRIPTION "I2O-subsystem"
49 * i2o_pci_free - Frees the DMA memory for the I2O controller
50 * @c: I2O controller to free
52 * Remove all allocated DMA memory and unmap memory IO regions. If MTRR
59 dev = &c->pdev->dev; in i2o_pci_free()
61 i2o_dma_free(dev, &c->out_queue); in i2o_pci_free()
62 i2o_dma_free(dev, &c->status_block); in i2o_pci_free()
63 kfree(c->lct); in i2o_pci_free()
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| /linux-3.3/arch/arm/plat-samsung/ |
| D | Kconfig | 1 # arch/arm/plat-samsung/Kconfig
45 int "S3C UART to use for low-level messages"
48 Choice of which UART port to use for the low-level messages,
51 must have been initialised by the boot-loader before use.
112 more memory.
169 Compile in platform device definition for I2C controller 3
174 Compile in platform device definition for I2C controller 4
179 Compile in platform device definition for I2C controller 5
184 Compile in platform device definition for I2C controller 6
189 Compile in platform device definition for I2C controller 7
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| /linux-3.3/Documentation/devicetree/bindings/ |
| D | marvell.txt | 1 Marvell Discovery mv64[345]6x System Controller chips
4 The Marvell mv64[345]60 series of system controller chips contain
7 the system controller chip itself and each of the peripherals
11 1) The /system-controller node
13 This node is used to represent the system-controller and must be
14 present when the system uses a system controller chip. The top-level
15 system-controller node contains information that is global to all
16 devices within the system controller chip. The node name begins
17 with "system-controller" followed by the unit address, which is
18 the base address of the memory-mapped register set for the system
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| /linux-3.3/Documentation/ |
| D | edac.txt | 3 EDAC - Error Detection And Correction
19 mailing list: bluesmoke-devel@lists.sourceforge.net
21 "bluesmoke" was the name for this device driver when it was "out-of-tree"
38 MEMORY
40 In the initial release, memory Correctable Errors (CE) and Uncorrectable
47 proactive part replacement of memory DIMMs exhibiting CEs can reduce
50 NON-MEMORY
55 This new device type allows for non-memory type of ECC hardware detectors
72 There are several add-in adapters that do NOT follow the PCI specification
106 EDAC is composed of a "core" module (edac_core.ko) and several Memory
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| D | DMA-ISA-LPC.txt | 7 controller. Even though ISA is more or less dead today the LPC bus
10 Part I - Headers and dependencies
11 ---------------------------------
15 #include <linux/dma-mapping.h>
19 physical addresses (see Documentation/DMA-API.txt for details).
26 Part II - Buffer allocation
27 ---------------------------
29 The ISA DMA controller has some very strict requirements on which
30 memory it can access so extra care must be taken when allocating
36 The DMA-able address space is the lowest 16 MB of _physical_ memory.
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| D | bus-virt-phys-mapping.txt | 3 (see Documentation/DMA-API-HOWTO.txt). They continue
5 must not use them. --davidm 00/12/12 ]
10 The AHA-1542 is a bus-master device, and your patch makes the driver give the
11 controller the physical address of the buffers, which is correct on x86
12 (because all bus master devices see the physical memory mappings directly).
15 at memory addresses, and in this case we actually want the third, the
16 so-called "bus address".
18 Essentially, the three ways of addressing memory are (this is "real memory",
19 that is, normal RAM--see later about other details):
21 - CPU untranslated. This is the "physical" address. Physical address
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| /linux-3.3/drivers/mmc/host/ |
| D | Kconfig | 2 # MMC/SD host controller drivers
5 comment "MMC/SD/SDIO Host Controller Drivers"
28 tristate "Secure Digital Host Controller Interface support"
31 This selects the generic Secure Digital Host Controller Interface.
35 If you have a controller with this interface, say Y or M here. You
45 need to overwrite SDHCI IO memory accessors.
52 and performing I/O to a SDHCI controller through a bus that
53 implements a hardware byte swapper using a 32-bit datum.
64 This selects the PCI Secure Digital Host Controller Interface.
67 If you have a controller with this interface, say Y or M here.
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| /linux-3.3/Documentation/blockdev/ |
| D | README.DAC960 | 14 Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
33 and DAC960PJ/PG/PU/PD/PL. See below for a complete controller list as well as
41 the controller's operation, and a detailed description of your system's
47 Please consult the RAID controller documentation for detailed information
64 of the controller and adding new disk drives, most everything can be handled
68 Each DAC960 parallel SCSI controller can support up to 15 disk drives per
69 channel, for a maximum of 60 drives on a four channel controller; the fibre
70 channel eXtremeRAID 3000 controller supports up to 125 disk drives per loop for
71 a total of 250 drives. The drives installed on a controller are divided into
82 System (DEVFS). The device corresponding to Logical Drive D on Controller C
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| /linux-3.3/arch/arm/mach-u300/include/mach/ |
| D | u300-regs.h | 3 * arch/arm/mach-u300/include/mach/u300-regs.h
6 * Copyright (C) 2006-2009 ST-Ericsson AB
8 * Basic register address definitions in physical memory and
17 * These are the large blocks of memory allocated for I/O.
18 * the defines are used for setting up the I/O memory mapping.
60 /* AHB Peripherals Bridge Controller */
63 /* Vectored Interrupt Controller 0, servicing 32 interrupts */
67 /* Vectored Interrupt Controller 1, servicing 32 interrupts */
71 /* Memory Stick Pro (MSPRO) controller */
85 /* MMC/SD controller */
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| /linux-3.3/arch/tile/kernel/ |
| D | pci.c | 38 * -------------------------------
74 return res->start; in pcibios_align_resource()
81 * controller_id is the controller number, config type is 0 or 1 for
101 struct pci_controller *controller) in tile_init_irqs() argument
113 return -1; in tile_init_irqs()
121 return -1; in tile_init_irqs()
124 controller->irq_base = rc_config.intr; in tile_init_irqs()
131 controller->plx_gen1 = 1; in tile_init_irqs()
150 /* Re-init number of PCIe controllers to support hot-plug feature. */ in tile_pci_init()
158 * the results of pcibios_init(), to support PCIe hot-plug. in tile_pci_init()
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| /linux-3.3/include/linux/ |
| D | edac.h | 6 * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
18 #define EDAC_OPSTATE_INVAL -1
48 /* memory devices */
69 /* memory types */
114 EDAC_EC, /* Error Checking - no correction */
116 EDAC_S2ECD2ED, /* Chipkill x2 devices - do these exist? */
155 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
168 * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
175 * Memory devices: The individual chip on a memory stick. These devices
178 * for a memory stick.
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| /linux-3.3/arch/arm/mach-bcmring/include/mach/ |
| D | irqs.h | 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 /* INTC0 - interrupt controller 0 */
55 #define IRQ_CLCD 30 /* LCD Controller interrupt */
59 /* INTC1 - interrupt controller 1 */
69 #define IRQ_FLASHC 40 /* 8 Flash controller interrupt */
76 #define IRQ_TSC 47 /* 15 Touch screen controller interrupt */
77 #define IRQ_KEYC 48 /* 16 Key pad controller interrupt */
78 #define IRQ_DMPU 49 /* 17 DDR2 memory partition interrupt */
79 #define IRQ_VMPU 50 /* 18 VRAM memory partition interrupt */
80 #define IRQ_FMPU 51 /* 19 Flash memory parition unit interrupt */
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| /linux-3.3/arch/ia64/pci/ |
| D | pci.c | 2 * pci.c - Low-Level PCI Access in IA-64
6 * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
7 * David Mosberger-Tang <davidm@hpl.hp.com>
35 * Low-level SAL-based PCI configuration access functions. Note that SAL
55 return -EINVAL; in raw_pci_read()
64 return -EINVAL; in raw_pci_read()
69 return -EINVAL; in raw_pci_read()
82 return -EINVAL; in raw_pci_write()
91 return -EINVAL; in raw_pci_write()
95 return -EINVAL; in raw_pci_write()
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| /linux-3.3/arch/powerpc/boot/dts/fsl/ |
| D | p1023si-post.dtsi | 36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus";
42 /* controller at 0xa000 */
44 compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0x0 0xff>;
49 clock-frequency = <33333333>;
53 #interrupt-cells = <1>;
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| /linux-3.3/init/ |
| D | Kconfig | 14 default "/etc/kernel-config"
15 default "/boot/config-$UNAME_RELEASE"
34 ---help---
39 known as the "alpha-test" phase among developers. If a feature is
40 currently in alpha-test, then the developers usually discourage
48 <file:README>, <file:MAINTAINERS>, <file:REPORTING-BUGS>,
49 <file:Documentation/BUG-HUNTING>, and
50 <file:Documentation/oops-tracing.txt> in the kernel source).
61 drivers that are currently considered to be in the alpha-test phase.
81 string "Cross-compiler tool prefix"
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