linux-3.3/Documentation/edac.txt

3 EDAC - Error Detection And Correction
19 	mailing list:	bluesmoke-devel@lists.sourceforge.net
21 "bluesmoke" was the name for this device driver when it was "out-of-tree"
38 MEMORY
40 In the initial release, memory Correctable Errors (CE) and Uncorrectable
47 proactive part replacement of memory DIMMs exhibiting CEs can reduce
50 NON-MEMORY
55 This new device type allows for non-memory type of ECC hardware detectors
72 There are several add-in adapters that do NOT follow the PCI specification
106 EDAC is composed of a "core" module (edac_core.ko) and several Memory
107 Controller (MC) driver modules. On a given system, the CORE
121 hardware-specific modules and have the dependencies load the necessary core
128 loads both the amd76x_edac.ko memory controller module and the edac_mc.ko
142 	mc	memory controller(s) system
147 Memory Controller (mc) Model
149 First a background on the memory controller's model abstracted in EDAC.
150 Each 'mc' device controls a set of DIMM memory modules. These modules are
151 laid out in a Chip-Select Row (csrowX) and Channel table (chX). There can
154 Memory controllers allow for several csrows, with 8 csrows being a typical value.
156 of a given motherboard, memory controller and DIMM characteristics.
158 Dual channels allows for 128 bit data transfers to the CPU from memory.
160 (FB-DIMMs). The following example will assume 2 channels:
175 for memory DIMMs:
186 based on the slot into which the memory DIMM is placed. Thus, when 1 DIMM
189 Memory DIMMs come single or dual "ranked". A rank is a populated csrow.
198 /sys/devices/system/edac/mc each memory controller will be represented
204 		   |->mc0
205 		   |->mc1
206 		   |->mc2
215 		|->csrow0
216 		|->csrow2
217 		|->csrow3
222 Channels, in order to have dual-channel mode be operational. Since
235 this 'X' instance of the memory controllers:
242 	This write-only control file will zero all the statistical counters
250 		This resets the counters on memory controller 0
263 Memory Controller name attribute file:
267 	This attribute file displays the type of memory controller
271 Total memory managed by this memory controller attribute file:
275 	This attribute file displays, in count of megabytes, of memory
276 	that this instance of memory controller manages.
284 	errors that have occurred on this memory controller. If panic_on_ue
302 	errors that have occurred on this memory controller. This
305 	field should be monitored for non-zero values and report
315 	is having errors. Memory is handicapped, but operational,
317 	the failing memory is in. This count field should be also
318 	be monitored for non-zero values.
324 	Symlink to the memory controller device.
326 Sdram memory scrubbing rate:
330 	Read/Write attribute file that controls memory scrubbing. The scrubbing
337 	If configuration fails or memory scrubbing is not implemented, the value
338 	of the attribute file will be -1.
367 	field should be monitored for non-zero values and report
371 Total memory managed by this csrow attribute file:
375 	This attribute file displays, in count of megabytes, of memory
379 Memory Type attribute file:
383 	This attribute file will display what type of memory is currently
384 	on this csrow. Normally, either buffered or unbuffered memory.
386 		Registered-DDR
387 		Unbuffered-DDR
490 	the memory controller			(MC0)
492 	memory page				(0x283)
497 	memory row				(row 0)
498 	memory channel				(channel 1)
500 	and then an optional, driver-specific message that may
503 Both UEs and CEs with no info will lack all but memory controller,
505 driver-specific error message.
558 	occurs - it is indeterminate what was uncorrected and the operating
646 	/sys/devices/systm/edac/test-instance
665 			One out-of-tree driver uses controls here to allow
675 	test-instance0
689 	test-block0
702 	test-block-bits-0	for every POLL cycle this counter
704 	test-block-bits-1	every 10 cycles, this counter is bumped once,
705 				and test-block-bits-0 is set to 0
706 	test-block-bits-2	every 100 cycles, this counter is bumped once,
707 				and test-block-bits-1 is set to 0
708 	test-block-bits-3	every 1000 cycles, this counter is bumped once,
709 				and test-block-bits-2 is set to 0
712 	reset-counters		writing ANY thing to this control will
729 Due to the way Nehalem exports Memory Controller data, some adjustments
732 1) On Nehalem, there are one Memory Controller per Quick Patch Interconnect
761    Each QPI is exported as a different memory controller.
766    For injecting a memory error, there are some sysfs nodes, under
773          rank = the memory rank;
802 		bit 0 - repeat
803 		bit 1 - ecc
804 		bit 2 - parity
830 …EDAC MC0: UE row 0, channel-a= 0 channel-b= 0 labels "-": NON_FATAL (addr = 0x0075b980, socket=0, …
832 3) Nehalem specific Corrected Error memory counters
834    Nehalem have some registers to count memory errors. The driver uses those
854    So, in this memory mapping: