include/linux/edac.h

6  * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
18 #define EDAC_OPSTATE_INVAL	-1
48 /* memory devices */
69 /* memory types */
114 	EDAC_EC,		/* Error Checking - no correction */
116 	EDAC_S2ECD2ED,		/* Chipkill x2 devices - do these exist? */
155 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
168  * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
175  * Memory devices:	The individual chip on a memory stick.  These devices
178  *			for a memory stick.
180  * Memory Stick:	A printed circuit board that aggregates multiple
181  *			memory devices in parallel.  This is the atomic
182  *			memory component that is purchaseable by Joe consumer
183  *			and loaded into a memory socket.
186  *			a single memory stick.
188  * Channel:		Set of memory devices on a memory stick that must be
190  *			channels from other memory sticks.  This parallel
192  *			necessary for the smallest granularity of memory access.
193  *			Some memory controllers are capable of single channel -
194  *			which means that memory sticks can be loaded
195  *			individually.  Other memory controllers are only
196  *			capable of dual channel - which means that memory
199  * Chip-select row:	All of the memory devices that are selected together.
200  *			for a single, minimum grain of memory access.
201  *			This selects all of the parallel memory devices across
202  *			all of the parallel channels.  Common chip-select rows
206  * Single-Ranked stick:	A Single-ranked stick has 1 chip-select row of memory.
207  *			Motherboards commonly drive two chip-select pins to
208  *			a memory stick. A single-ranked stick, will occupy
211  * Double-Ranked stick:	A double-ranked stick has two chip-select rows which
212  *			access different sets of memory devices.  The two
215  * Double-sided stick:	DEPRECATED TERM, see Double-Ranked stick.
216  *			A double-sided stick has two chip-select rows which
217  *			access different sets of memory devices.  The two
218  *			rows cannot be accessed concurrently.  "Double-sided"
219  *			is irrespective of the memory devices being mounted
220  *			on both sides of the memory stick.
222  * Socket set:		All of the memory sticks that are required for
223  *			a single memory access or all of the memory sticks
224  *			spanned by a chip-select row.  A single socket set
225  *			has two chip-select rows and if double-sided sticks
226  *			are used these will occupy those chip-select rows.
229  *			needing to distinguish between chip-select rows and
232  * Controller pages:
243  * PS - I enjoyed writing all that about as much as you enjoyed reading it.
256 	unsigned long page_mask;	/* used for interleaving -
261 	int csrow_idx;		/* the chip-select row */
262 	enum dev_type dtype;	/* memory device type */
265 	enum mem_type mtype;	/* memory csrow type */
299 	/* Ops for show/store values at the attribute - not used on group */
304 /* MEMORY controller information structure
311 	unsigned long mtype_cap;	/* memory types supported by mc */
312 	unsigned long edac_ctl_cap;	/* Mem controller EDAC capabilities */
313 	unsigned long edac_cap;	/* configuration capabilities - this is
315 				 * difference is that the controller may be
324 	/* Translates sdram memory scrub rate given in bytes/sec to the
330 	/* Get the current sdram memory scrub rate from the internal
341 	 * Remaps memory pages: controller pages to physical pages.
344 	/* FIXME - why not send the phys page to begin with? */
351 	 * FIXME - what about controllers on other busses? - IDs must be
376 	/* Additional top controller level attributes, but specified
380 	 * controller level, same level as 'ue_count' and 'ce_count' above.
391 	/* the internal state of this controller instance */