Lines Matching +full:memory +full:- +full:controller
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 /* INTC0 - interrupt controller 0 */
55 #define IRQ_CLCD 30 /* LCD Controller interrupt */
59 /* INTC1 - interrupt controller 1 */
69 #define IRQ_FLASHC 40 /* 8 Flash controller interrupt */
76 #define IRQ_TSC 47 /* 15 Touch screen controller interrupt */
77 #define IRQ_KEYC 48 /* 16 Key pad controller interrupt */
78 #define IRQ_DMPU 49 /* 17 DDR2 memory partition interrupt */
79 #define IRQ_VMPU 50 /* 18 VRAM memory partition interrupt */
80 #define IRQ_FMPU 51 /* 19 Flash memory parition unit interrupt */
83 #define IRQ_RTC1 54 /* 22 Real time clock one-shot interrupt */
90 /* SINTC secure int controller */
94 #define IRQ_SEC_TSC 61 /* 2 Touch screen controller interrupt */
95 #define IRQ_SEC_KEYC 62 /* 3 Key pad controller interrupt */
96 #define IRQ_SEC_DMPU 63 /* 4 DDR2 memory partition interrupt */
97 #define IRQ_SEC_VMPU 64 /* 5 VRAM memory partition interrupt */
98 #define IRQ_SEC_FMPU 65 /* 6 Flash memory parition unit interrupt */
101 #define IRQ_SEC_RTC1 68 /* 9 Real time clock one-shot interrupt */
111 /* Note: there are 3 INTC registers of 32 bits each. So internal IRQs could go from 0-95 */
125 #define IRQ_UNKNOWN -1