Lines Matching +full:memory +full:- +full:controller
29 * associated with the IMB DDR2 ECC controller found in the AMCC/IBM
32 * As realized in the 405EX[r], this controller features:
34 * - Support for registered- and non-registered DDR1 and DDR2 memory.
35 * - 32-bit or 16-bit memory interface with optional ECC.
39 * - 4-bit SEC/DED
40 * - Aligned-nibble error detect
41 * - Bypass mode
43 * - Two (2) memory banks/ranks.
44 * - Up to 1 GiB per bank/rank in 32-bit mode and up to 512 MiB per
45 * bank/rank in 16-bit mode.
47 * As realized in the 440SP and 440SPe, this controller changes/adds:
49 * - 64-bit or 32-bit memory interface with optional ECC.
53 * - 8-bit SEC/DED
54 * - Aligned-nibble error detect
55 * - Bypass mode
57 * - Up to 4 GiB per bank/rank in 64-bit mode and up to 2 GiB
58 * per bank/rank in 32-bit mode.
60 * As realized in the 460EX and 460GT, this controller changes/adds:
62 * - 64-bit or 32-bit memory interface with optional ECC.
66 * - 8-bit SEC/DED
67 * - Aligned-nibble error detect
68 * - Bypass mode
70 * - Four (4) memory banks/ranks.
71 * - Up to 16 GiB per bank/rank in 64-bit mode and up to 8 GiB
72 * per bank/rank in 32-bit mode.
74 * At present, this driver has ONLY been tested against the controller
76 * boards (256 MiB w/o ECC memory soldered onto the board) and a
77 * proprietary board based on those designs (128 MiB ECC memory, also
81 * other realizations of this controller listed above.
84 * realizations of this controller as well as broken apart to handle
85 * the other known ECC-capable controllers prevalent in other 4xx
88 * - IBM SDRAM (405GP, 405CR and 405EP) "ibm,sdram-4xx"
89 * - IBM DDR1 (440GP, 440GX, 440EP and 440GR) "ibm,sdram-4xx-ddr"
90 * - Denali DDR1/DDR2 (440EPX and 440GRX) "denali,sdram-4xx-ddr2"
92 * For this controller, unfortunately, correctable errors report
100 * following pieces of information in the driver-unique message to the
103 * - Device tree path
104 * - Bank(s)
105 * - Check bit error group
106 * - Beat(s)/lane(s)
140 << (20 - PAGE_SHIFT + \
144 * The ibm,sdram-4xx-ddr2 Device Control Registers (DCRs) are
157 #define INTMAP_ECCDED_INDEX 0 /* Double-bit Error Detect */
158 #define INTMAP_ECCSEC_INDEX 1 /* Single-bit Error Correct */
163 * PPC4xx SDRAM memory controller private instance data
168 int sec; /* Single-bit correctable error IRQ assigned */
169 int ded; /* Double-bit detectable error IRQ assigned */
198 .compatible = "ibm,sdram-4xx-ddr2"
215 * set based on the aforementioned variant controller realizations.
226 [SDRAM_PLB_M0ID_PCIE0] = "PCI-E 0",
227 [SDRAM_PLB_M0ID_PCIE1] = "PCI-E 1",
237 * mfsdram - read and return controller register data
242 * controller's specified indirect DCR register.
249 return __mfdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET, in mfsdram()
250 dcr_host->base + SDRAM_DCR_DATA_OFFSET, in mfsdram()
255 * mtsdram - write controller register data
260 * This routine writes the provided data to the controller's specified
266 return __mtdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET, in mtsdram()
267 dcr_host->base + SDRAM_DCR_DATA_OFFSET, in mtsdram()
273 * ppc4xx_edac_check_bank_error - check a bank for an ECC bank error
290 return status->ecces & SDRAM_ECCES_BK0ER; in ppc4xx_edac_check_bank_error()
292 return status->ecces & SDRAM_ECCES_BK1ER; in ppc4xx_edac_check_bank_error()
299 * ppc4xx_edac_generate_bank_message - generate interpretted bank status message
300 * @mci: A pointer to the EDAC memory controller instance associated
309 * driver-unique report message associated with the ECCESS[BKNER]
324 n = snprintf(buffer, size, "%s: Banks: ", mci->dev_name); in ppc4xx_edac_generate_bank_message()
330 size -= n; in ppc4xx_edac_generate_bank_message()
333 for (rows = 0, row = 0; row < mci->nr_csrows; row++) { in ppc4xx_edac_generate_bank_message()
342 size -= n; in ppc4xx_edac_generate_bank_message()
353 size -= n; in ppc4xx_edac_generate_bank_message()
361 * ppc4xx_edac_generate_checkbit_message - generate interpretted checkbit message
362 * @mci: A pointer to the EDAC memory controller instance associated
371 * driver-unique report message associated with the ECCESS[CKBER]
383 const struct ppc4xx_edac_pdata *pdata = mci->pvt_info; in ppc4xx_edac_generate_checkbit_message()
386 switch (status->ecces & SDRAM_ECCES_CKBER_MASK) { in ppc4xx_edac_generate_checkbit_message()
394 switch (mfsdram(&pdata->dcr_host, SDRAM_MCOPT1) & in ppc4xx_edac_generate_checkbit_message()
419 * ppc4xx_edac_generate_lane_message - generate interpretted byte lane message
420 * @mci: A pointer to the EDAC memory controller instance associated
429 * driver-unique report message associated with the ECCESS[BNCE]
452 size -= n; in ppc4xx_edac_generate_lane_message()
456 if ((status->ecces & SDRAM_ECCES_BNCE_ENCODE(lane)) != 0) { in ppc4xx_edac_generate_lane_message()
465 size -= n; in ppc4xx_edac_generate_lane_message()
476 size -= n; in ppc4xx_edac_generate_lane_message()
484 * ppc4xx_edac_generate_ecc_message - generate interpretted ECC status message
485 * @mci: A pointer to the EDAC memory controller instance associated
494 * driver-unique report message associated with the ECCESS register of
514 size -= n; in ppc4xx_edac_generate_ecc_message()
523 size -= n; in ppc4xx_edac_generate_ecc_message()
532 size -= n; in ppc4xx_edac_generate_ecc_message()
540 * ppc4xx_edac_generate_plb_message - generate interpretted PLB status message
541 * @mci: A pointer to the EDAC memory controller instance associated
550 * driver-unique report message associated with the PLB-related BESR
565 if ((status->besr & SDRAM_BESR_MASK) == 0) in ppc4xx_edac_generate_plb_message()
568 if ((status->besr & SDRAM_BESR_M0ET_MASK) == SDRAM_BESR_M0ET_NONE) in ppc4xx_edac_generate_plb_message()
571 read = ((status->besr & SDRAM_BESR_M0RW_MASK) == SDRAM_BESR_M0RW_READ); in ppc4xx_edac_generate_plb_message()
573 master = SDRAM_BESR_M0ID_DECODE(status->besr); in ppc4xx_edac_generate_plb_message()
585 * ppc4xx_edac_generate_message - generate interpretted status message
586 * @mci: A pointer to the EDAC memory controller instance associated
587 * with the driver-unique message being generated.
594 * This routine generates to the provided buffer the driver-unique
614 size -= n; in ppc4xx_edac_generate_message()
621 * ppc4xx_ecc_dump_status - dump controller ECC status registers
622 * @mci: A pointer to the EDAC memory controller instance
645 status->ecces, in ppc4xx_ecc_dump_status()
646 status->wmirq, in ppc4xx_ecc_dump_status()
647 status->besr, in ppc4xx_ecc_dump_status()
648 status->bearh, in ppc4xx_ecc_dump_status()
649 status->bearl, in ppc4xx_ecc_dump_status()
655 * ppc4xx_ecc_get_status - get controller ECC status
656 * @mci: A pointer to the EDAC memory controller instance
662 * status registers that deal with ibm,sdram-4xx-ddr2 ECC errors.
671 const struct ppc4xx_edac_pdata *pdata = mci->pvt_info; in ppc4xx_ecc_get_status()
672 const dcr_host_t *dcr_host = &pdata->dcr_host; in ppc4xx_ecc_get_status()
674 status->ecces = mfsdram(dcr_host, SDRAM_ECCES) & SDRAM_ECCES_MASK; in ppc4xx_ecc_get_status()
675 status->wmirq = mfsdram(dcr_host, SDRAM_WMIRQ) & SDRAM_WMIRQ_MASK; in ppc4xx_ecc_get_status()
676 status->besr = mfsdram(dcr_host, SDRAM_BESR) & SDRAM_BESR_MASK; in ppc4xx_ecc_get_status()
677 status->bearl = mfsdram(dcr_host, SDRAM_BEARL); in ppc4xx_ecc_get_status()
678 status->bearh = mfsdram(dcr_host, SDRAM_BEARH); in ppc4xx_ecc_get_status()
682 * ppc4xx_ecc_clear_status - clear controller ECC status
683 * @mci: A pointer to the EDAC memory controller instance
688 * This routine clears--by writing the masked (as appropriate) status
689 * values back to--the status registers that deal with
690 * ibm,sdram-4xx-ddr2 ECC errors.
696 const struct ppc4xx_edac_pdata *pdata = mci->pvt_info; in ppc4xx_ecc_clear_status()
697 const dcr_host_t *dcr_host = &pdata->dcr_host; in ppc4xx_ecc_clear_status()
699 mtsdram(dcr_host, SDRAM_ECCES, status->ecces & SDRAM_ECCES_MASK); in ppc4xx_ecc_clear_status()
700 mtsdram(dcr_host, SDRAM_WMIRQ, status->wmirq & SDRAM_WMIRQ_MASK); in ppc4xx_ecc_clear_status()
701 mtsdram(dcr_host, SDRAM_BESR, status->besr & SDRAM_BESR_MASK); in ppc4xx_ecc_clear_status()
707 * ppc4xx_edac_handle_ce - handle controller correctable ECC error (CE)
708 * @mci: A pointer to the EDAC memory controller instance
713 * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
716 * interface, so we just pass driver-unique message to the "no info"
728 for (row = 0; row < mci->nr_csrows; row++) in ppc4xx_edac_handle_ce()
734 * ppc4xx_edac_handle_ue - handle controller uncorrectable ECC error (UE)
735 * @mci: A pointer to the EDAC memory controller instance
741 * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
748 const u64 bear = ((u64)status->bearh << 32 | status->bearl); in ppc4xx_edac_handle_ue()
756 for (row = 0; row < mci->nr_csrows; row++) in ppc4xx_edac_handle_ue()
762 * ppc4xx_edac_check - check controller for ECC errors
763 * @mci: A pointer to the EDAC memory controller instance
764 * associated with the ibm,sdram-4xx-ddr2 controller being
796 * ppc4xx_edac_isr - SEC (CE) and DED (UE) interrupt service routine
798 * @dev_id: A pointer to the EDAC memory controller instance
802 * (CE) and uncorrectable (UE) ECC errors for the ibm,sdram-4xx-ddr2
803 * controller. It simply calls through to the same routine used during
819 * ppc4xx_edac_get_dtype - return the controller memory width
820 * @mcopt1: The 32-bit Memory Controller Option 1 register value
821 * currently set for the controller, from which the width
825 * current controller configuration.
828 * flags or some such when other controller variants are supported as
829 * the 405EX[r] is 16-/32-bit and the others are 32-/64-bit with the
830 * 16- and 64-bit field definition/value/enumeration (b1) overloaded
849 * ppc4xx_edac_get_mtype - return controller memory type
850 * @mcopt1: The 32-bit Memory Controller Option 1 register value
851 * currently set for the controller, from which the memory type
854 * This routine returns the EDAC memory type appropriate for the
855 * current controller configuration.
857 * Returns a memory type enumeration.
875 * ppc4xx_edac_init_csrows - initialize driver instance rows
876 * @mci: A pointer to the EDAC memory controller instance
877 * associated with the ibm,sdram-4xx-ddr2 controller for which
879 * @mcopt1: The 32-bit Memory Controller Option 1 register value
880 * currently set for the controller, from which bank width
881 * and memory typ information is derived.
884 * with the EDAC memory controller instance. An ibm,sdram-4xx-ddr2
885 * controller bank/rank is mapped to a row.
887 * Returns 0 if OK; otherwise, -EINVAL if the memory bank size
893 const struct ppc4xx_edac_pdata *pdata = mci->pvt_info; in ppc4xx_edac_init_csrows()
902 /* Establish the memory type and width */ in ppc4xx_edac_init_csrows()
909 if (mci->edac_cap & EDAC_FLAG_SECDED) in ppc4xx_edac_init_csrows()
911 else if (mci->edac_cap & EDAC_FLAG_EC) in ppc4xx_edac_init_csrows()
918 * 1:1 with a controller bank/rank. in ppc4xx_edac_init_csrows()
921 for (row = 0; row < mci->nr_csrows; row++) { in ppc4xx_edac_init_csrows()
922 struct csrow_info *csi = &mci->csrows[row]; in ppc4xx_edac_init_csrows()
929 mbxcf = mfsdram(&pdata->dcr_host, SDRAM_MBXCF(row)); in ppc4xx_edac_init_csrows()
951 csi->nr_pages = SDRAM_MBCF_SZ_TO_PAGES(size); in ppc4xx_edac_init_csrows()
955 "Unrecognized memory bank %d " in ppc4xx_edac_init_csrows()
958 status = -EINVAL; in ppc4xx_edac_init_csrows()
962 csi->first_page = ppc4xx_last_page; in ppc4xx_edac_init_csrows()
963 csi->last_page = csi->first_page + csi->nr_pages - 1; in ppc4xx_edac_init_csrows()
964 csi->page_mask = 0; in ppc4xx_edac_init_csrows()
976 * page size (PAGE_SIZE) or the memory width (2 or 4). in ppc4xx_edac_init_csrows()
979 csi->grain = 1; in ppc4xx_edac_init_csrows()
981 csi->mtype = mtype; in ppc4xx_edac_init_csrows()
982 csi->dtype = dtype; in ppc4xx_edac_init_csrows()
984 csi->edac_mode = edac_mode; in ppc4xx_edac_init_csrows()
986 ppc4xx_last_page += csi->nr_pages; in ppc4xx_edac_init_csrows()
994 * ppc4xx_edac_mc_init - initialize driver instance
995 * @mci: A pointer to the EDAC memory controller instance being
998 * with the controller this EDAC instance is bound to.
1000 * for this controller instance.
1001 * @mcopt1: The 32-bit Memory Controller Option 1 register value
1002 * currently set for the controller, from which ECC capabilities
1005 * This routine performs initialization of the EDAC memory controller
1006 * instance and related driver-private data associated with the
1007 * ibm,sdram-4xx-ddr2 memory controller the instance is bound to.
1020 const struct device_node *np = op->dev.of_node; in ppc4xx_edac_mc_init()
1022 if (of_match_device(ppc4xx_edac_match, &op->dev) == NULL) in ppc4xx_edac_mc_init()
1023 return -EINVAL; in ppc4xx_edac_mc_init()
1027 mci->dev = &op->dev; in ppc4xx_edac_mc_init()
1029 dev_set_drvdata(mci->dev, mci); in ppc4xx_edac_mc_init()
1031 pdata = mci->pvt_info; in ppc4xx_edac_mc_init()
1033 pdata->dcr_host = *dcr_host; in ppc4xx_edac_mc_init()
1034 pdata->irqs.sec = NO_IRQ; in ppc4xx_edac_mc_init()
1035 pdata->irqs.ded = NO_IRQ; in ppc4xx_edac_mc_init()
1037 /* Initialize controller capabilities and configuration */ in ppc4xx_edac_mc_init()
1039 mci->mtype_cap = (MEM_FLAG_DDR | MEM_FLAG_RDDR | in ppc4xx_edac_mc_init()
1042 mci->edac_ctl_cap = (EDAC_FLAG_NONE | in ppc4xx_edac_mc_init()
1046 mci->scrub_cap = SCRUB_NONE; in ppc4xx_edac_mc_init()
1047 mci->scrub_mode = SCRUB_NONE; in ppc4xx_edac_mc_init()
1056 mci->edac_cap = EDAC_FLAG_EC; in ppc4xx_edac_mc_init()
1059 mci->edac_cap = (EDAC_FLAG_EC | EDAC_FLAG_SECDED); in ppc4xx_edac_mc_init()
1060 mci->scrub_mode = SCRUB_SW_SRC; in ppc4xx_edac_mc_init()
1063 mci->edac_cap = EDAC_FLAG_NONE; in ppc4xx_edac_mc_init()
1069 mci->mod_name = PPC4XX_EDAC_MODULE_NAME; in ppc4xx_edac_mc_init()
1070 mci->mod_ver = PPC4XX_EDAC_MODULE_REVISION; in ppc4xx_edac_mc_init()
1071 mci->ctl_name = match->compatible, in ppc4xx_edac_mc_init()
1072 mci->dev_name = np->full_name; in ppc4xx_edac_mc_init()
1076 mci->edac_check = ppc4xx_edac_check; in ppc4xx_edac_mc_init()
1077 mci->ctl_page_to_phys = NULL; in ppc4xx_edac_mc_init()
1091 * ppc4xx_edac_register_irq - setup and register controller interrupts
1093 * with the controller this EDAC instance is bound to.
1094 * @mci: A pointer to the EDAC memory controller instance
1095 * associated with the ibm,sdram-4xx-ddr2 controller for which
1100 * the associated EDAC memory controller instance.
1102 * Returns 0 if OK; otherwise, -ENODEV if the interrupts could not be
1110 struct ppc4xx_edac_pdata *pdata = mci->pvt_info; in ppc4xx_edac_register_irq()
1111 struct device_node *np = op->dev.of_node; in ppc4xx_edac_register_irq()
1119 status = -ENODEV; in ppc4xx_edac_register_irq()
1133 status = -ENODEV; in ppc4xx_edac_register_irq()
1147 status = -ENODEV; in ppc4xx_edac_register_irq()
1154 pdata->irqs.ded = ded_irq; in ppc4xx_edac_register_irq()
1155 pdata->irqs.sec = sec_irq; in ppc4xx_edac_register_irq()
1170 * ppc4xx_edac_map_dcrs - locate and map controller registers
1177 * register resources associated with the controller's indirect DCR
1189 return -EINVAL; in ppc4xx_edac_map_dcrs()
1199 return -ENODEV; in ppc4xx_edac_map_dcrs()
1206 return -ENODEV; in ppc4xx_edac_map_dcrs()
1215 return -ENODEV; in ppc4xx_edac_map_dcrs()
1222 * ppc4xx_edac_probe - check controller and bind driver
1224 * with the controller being probed for driver binding.
1226 * This routine probes a specific ibm,sdram-4xx-ddr2 controller
1229 * Returns 0 if the controller instance was successfully bound to the
1237 const struct device_node *np = op->dev.of_node; in ppc4xx_edac_probe()
1242 * At this point, we only support the controller realized on in ppc4xx_edac_probe()
1246 if (!of_device_is_compatible(np, "ibm,sdram-405ex") && in ppc4xx_edac_probe()
1247 !of_device_is_compatible(np, "ibm,sdram-405exr")) { in ppc4xx_edac_probe()
1250 return -ENODEV; in ppc4xx_edac_probe()
1255 * can probe the controller. in ppc4xx_edac_probe()
1266 * for this controller. in ppc4xx_edac_probe()
1273 ppc4xx_edac_printk(KERN_INFO, "%s: No ECC memory detected or " in ppc4xx_edac_probe()
1274 "ECC is disabled.\n", np->full_name); in ppc4xx_edac_probe()
1275 status = -ENODEV; in ppc4xx_edac_probe()
1281 * controller instance and perform the appropriate in ppc4xx_edac_probe()
1293 np->full_name); in ppc4xx_edac_probe()
1294 status = -ENOMEM; in ppc4xx_edac_probe()
1308 * controller. Attempt to register it with the EDAC subsystem in ppc4xx_edac_probe()
1315 status = -ENODEV; in ppc4xx_edac_probe()
1331 edac_mc_del_mc(mci->dev); in ppc4xx_edac_probe()
1341 * ppc4xx_edac_remove - unbind driver from controller
1343 * with the controller this EDAC instance is to be unbound/removed
1346 * This routine unbinds the EDAC memory controller instance associated
1347 * with the specified ibm,sdram-4xx-ddr2 controller described by the
1355 struct mem_ctl_info *mci = dev_get_drvdata(&op->dev); in ppc4xx_edac_remove()
1356 struct ppc4xx_edac_pdata *pdata = mci->pvt_info; in ppc4xx_edac_remove()
1359 free_irq(pdata->irqs.sec, mci); in ppc4xx_edac_remove()
1360 free_irq(pdata->irqs.ded, mci); in ppc4xx_edac_remove()
1363 dcr_unmap(pdata->dcr_host, SDRAM_DCR_RESOURCE_LEN); in ppc4xx_edac_remove()
1365 edac_mc_del_mc(mci->dev); in ppc4xx_edac_remove()
1372 * ppc4xx_edac_opstate_init - initialize EDAC reporting method
1374 * This routine ensures that the EDAC memory controller reporting
1401 * ppc4xx_edac_init - driver/module insertion entry point
1404 * initializes the EDAC memory controller reporting state and
1419 * ppc4xx_edac_exit - driver/module removal entry point
1436 MODULE_DESCRIPTION("EDAC MC Driver for the PPC4xx IBM DDR2 Memory Controller");