2  * pci.c - Low-Level PCI Access in IA-64
6  * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
7  *	David Mosberger-Tang <davidm@hpl.hp.com>
35  * Low-level SAL-based PCI configuration access functions. Note that SAL
55 		return -EINVAL;  in raw_pci_read()
64 		return -EINVAL;  in raw_pci_read()
69 		return -EINVAL;  in raw_pci_read()
82 		return -EINVAL;  in raw_pci_write()
91 		return -EINVAL;  in raw_pci_write()
95 		return -EINVAL;  in raw_pci_write()
102 	return raw_pci_read(pci_domain_nr(bus), bus->number,  in pci_read()
109 	return raw_pci_write(pci_domain_nr(bus), bus->number,  in pci_write()
123 	struct pci_controller *controller;  in alloc_pci_controller()  local
125 	controller = kzalloc(sizeof(*controller), GFP_KERNEL);  in alloc_pci_controller()
126 	if (!controller)  in alloc_pci_controller()
129 	controller->segment = seg;  in alloc_pci_controller()
130 	controller->node = -1;  in alloc_pci_controller()
131 	return controller;  in alloc_pci_controller()
136 	struct pci_controller *controller;  member
179 		printk(KERN_ERR "PCI: No memory for %s I/O port space\n",  in add_io_space()
180 			info->name);  in add_io_space()
184 	len = strlen(info->name) + 32;  in add_io_space()
187 		printk(KERN_ERR "PCI: No memory for %s I/O port space name\n",  in add_io_space()
188 			info->name);  in add_io_space()
192 	min = addr->minimum;  in add_io_space()
193 	max = min + addr->address_length - 1;  in add_io_space()
194 	if (addr->info.io.translation_type == ACPI_SPARSE_TRANSLATION)  in add_io_space()
197 	space_nr = new_space(addr->translation_offset, sparse);  in add_io_space()
203 	snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->name,  in add_io_space()
207 	 * The SDM guarantees the legacy 0-64K space is sparse, but if the  in add_io_space()
214 	resource->name  = name;  in add_io_space()
215 	resource->flags = IORESOURCE_MEM;  in add_io_space()
216 	resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min);  in add_io_space()
217 	resource->end   = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max);  in add_io_space()
237 	 *	- address space descriptors for memory or I/O space  in resource_to_window()
238 	 *	- non-zero size  in resource_to_window()
239 	 *	- producers, i.e., the address space is routed downstream,  in resource_to_window()
244 	    (addr->resource_type == ACPI_MEMORY_RANGE ||  in resource_to_window()
245 	     addr->resource_type == ACPI_IO_RANGE) &&  in resource_to_window()
246 	    addr->address_length &&  in resource_to_window()
247 	    addr->producer_consumer == ACPI_PRODUCER)  in resource_to_window()
276 	/* Return AE_OK for non-window resources to keep scanning for more */  in add_window()
294 	window = &info->controller->window[info->controller->windows++];  in add_window()
295 	window->resource.name = info->name;  in add_window()
296 	window->resource.flags = flags;  in add_window()
297 	window->resource.start = addr.minimum + offset;  in add_window()
298 	window->resource.end = window->resource.start + addr.address_length - 1;  in add_window()
299 	window->resource.child = NULL;  in add_window()
300 	window->offset = offset;  in add_window()
302 	if (insert_resource(root, &window->resource)) {  in add_window()
303 		dev_err(&info->bridge->dev,  in add_window()
305 			&window->resource);  in add_window()
308 			dev_info(&info->bridge->dev, "host bridge window %pR "  in add_window()
309 				 "(PCI address [%#llx-%#llx])\n",  in add_window()
310 				 &window->resource,  in add_window()
311 				 window->resource.start - offset,  in add_window()
312 				 window->resource.end - offset);  in add_window()
314 			dev_info(&info->bridge->dev,  in add_window()
316 				 &window->resource);  in add_window()
320 	 * Ignore these tiny memory ranges */  in add_window()
321 	if (!((window->resource.flags & IORESOURCE_MEM) &&  in add_window()
322 	      (window->resource.end - window->resource.start < 16)))  in add_window()
323 		pci_add_resource(&info->resources, &window->resource);  in add_window()
331 	struct acpi_device *device = root->device;  in pci_acpi_scan_root()
332 	int domain = root->segment;  in pci_acpi_scan_root()
333 	int bus = root->secondary.start;  in pci_acpi_scan_root()
334 	struct pci_controller *controller;  in pci_acpi_scan_root()  local
341 	controller = alloc_pci_controller(domain);  in pci_acpi_scan_root()
342 	if (!controller)  in pci_acpi_scan_root()
345 	controller->acpi_handle = device->handle;  in pci_acpi_scan_root()
347 	pxm = acpi_get_pxm(controller->acpi_handle);  in pci_acpi_scan_root()
350 		controller->node = pxm_to_node(pxm);  in pci_acpi_scan_root()
354 	acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,  in pci_acpi_scan_root()
357 		controller->window =  in pci_acpi_scan_root()
358 			kmalloc_node(sizeof(*controller->window) * windows,  in pci_acpi_scan_root()
359 				     GFP_KERNEL, controller->node);  in pci_acpi_scan_root()
360 		if (!controller->window)  in pci_acpi_scan_root()
369 		info.controller = controller;  in pci_acpi_scan_root()
371 		acpi_walk_resources(device->handle, METHOD_NAME__CRS,  in pci_acpi_scan_root()
380 	pbus = pci_create_root_bus(NULL, bus, &pci_root_ops, controller,  in pci_acpi_scan_root()
387 	pbus->subordinate = pci_scan_child_bus(pbus);  in pci_acpi_scan_root()
391 	kfree(controller->window);  in pci_acpi_scan_root()
393 	kfree(controller);  in pci_acpi_scan_root()
401 	struct pci_controller *controller = PCI_CONTROLLER(dev);  in pcibios_resource_to_bus()  local
405 	for (i = 0; i < controller->windows; i++) {  in pcibios_resource_to_bus()
406 		struct pci_window *window = &controller->window[i];  in pcibios_resource_to_bus()
407 		if (!(window->resource.flags & res->flags))  in pcibios_resource_to_bus()
409 		if (window->resource.start > res->start)  in pcibios_resource_to_bus()
411 		if (window->resource.end < res->end)  in pcibios_resource_to_bus()
413 		offset = window->offset;  in pcibios_resource_to_bus()
417 	region->start = res->start - offset;  in pcibios_resource_to_bus()
418 	region->end = res->end - offset;  in pcibios_resource_to_bus()
425 	struct pci_controller *controller = PCI_CONTROLLER(dev);  in pcibios_bus_to_resource()  local
429 	for (i = 0; i < controller->windows; i++) {  in pcibios_bus_to_resource()
430 		struct pci_window *window = &controller->window[i];  in pcibios_bus_to_resource()
431 		if (!(window->resource.flags & res->flags))  in pcibios_bus_to_resource()
433 		if (window->resource.start - window->offset > region->start)  in pcibios_bus_to_resource()
435 		if (window->resource.end - window->offset < region->end)  in pcibios_bus_to_resource()
437 		offset = window->offset;  in pcibios_bus_to_resource()
441 	res->start = region->start + offset;  in pcibios_bus_to_resource()
442 	res->end = region->end + offset;  in pcibios_bus_to_resource()
449 	struct resource *devr = &dev->resource[idx], *busr;  in is_valid_resource()
451 	if (!dev->bus)  in is_valid_resource()
454 	pci_bus_for_each_resource(dev->bus, busr, i) {  in is_valid_resource()
455 		if (!busr || ((busr->flags ^ devr->flags) & type_mask))  in is_valid_resource()
457 		if ((devr->start) && (devr->start >= busr->start) &&  in is_valid_resource()
458 				(devr->end <= busr->end))  in is_valid_resource()
471 		if (!dev->resource[i].flags)  in pcibios_fixup_resources()
473 		region.start = dev->resource[i].start;  in pcibios_fixup_resources()
474 		region.end = dev->resource[i].end;  in pcibios_fixup_resources()
475 		pcibios_bus_to_resource(dev, &dev->resource[i], &region);  in pcibios_fixup_resources()
500 	if (b->self) {  in pcibios_fixup_bus()
502 		pcibios_fixup_bridge_resources(b->self);  in pcibios_fixup_bus()
504 	list_for_each_entry(dev, &b->devices, bus_list)  in pcibios_fixup_bus()
519 	/* ??? FIXME -- record old value for shutdown.  */  in pcibios_update_irq()
531 	if (!dev->msi_enabled)  in pcibios_enable_device()
539 	BUG_ON(atomic_read(&dev->enable_cnt));  in pcibios_disable_device()
540 	if (!dev->msi_enabled)  in pcibios_disable_device()
548 	return res->start;  in pcibios_align_resource()
564 	unsigned long size = vma->vm_end - vma->vm_start;  in pci_mmap_page_range()
574 		 * indicates that the space is 1-to-1 mapped.  But at the  in pci_mmap_page_range()
576 		 * the legacy I/O space is not 1-to-1 mapped, so this is moot.  in pci_mmap_page_range()
578 		return -EINVAL;  in pci_mmap_page_range()
580 	if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))  in pci_mmap_page_range()
581 		return -EINVAL;  in pci_mmap_page_range()
583 	prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size,  in pci_mmap_page_range()
584 				    vma->vm_page_prot);  in pci_mmap_page_range()
594 	    efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start))  in pci_mmap_page_range()
595 		vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);  in pci_mmap_page_range()
597 		vma->vm_page_prot = prot;  in pci_mmap_page_range()
599 	if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,  in pci_mmap_page_range()
600 			     vma->vm_end - vma->vm_start, vma->vm_page_prot))  in pci_mmap_page_range()
601 		return -EAGAIN;  in pci_mmap_page_range()
607  * ia64_pci_get_legacy_mem - generic legacy mem routine
608  * @bus: bus to get legacy memory base address for
610  * Find the base of legacy memory for @bus.  This is typically the first
612  * chipsets support legacy I/O and memory routing.  Returns the base address
624  * pci_mmap_legacy_page_range - map legacy memory space to userland
628  * Map legacy memory space for this device back to userspace using a machine
635 	unsigned long size = vma->vm_end - vma->vm_start;  in pci_mmap_legacy_page_range()
639 	/* We only support mmap'ing of legacy memory space */  in pci_mmap_legacy_page_range()
641 		return -ENOSYS;  in pci_mmap_legacy_page_range()
647 	if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))  in pci_mmap_legacy_page_range()
648 		return -EINVAL;  in pci_mmap_legacy_page_range()
649 	prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size,  in pci_mmap_legacy_page_range()
650 				    vma->vm_page_prot);  in pci_mmap_legacy_page_range()
656 	vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT;  in pci_mmap_legacy_page_range()
657 	vma->vm_page_prot = prot;  in pci_mmap_legacy_page_range()
659 	if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,  in pci_mmap_legacy_page_range()
660 			    size, vma->vm_page_prot))  in pci_mmap_legacy_page_range()
661 		return -EAGAIN;  in pci_mmap_legacy_page_range()
667  * ia64_pci_legacy_read - read from legacy I/O space
694 		ret = -EINVAL;  in ia64_pci_legacy_read()
702  * ia64_pci_legacy_write - perform a legacy I/O write
725 		ret = -EINVAL;  in ia64_pci_legacy_write()
733  * set_pci_cacheline_size - determine cacheline size for PCI devices
735  * We want to use the line-size of the outer-most cache.  We assume
736  * that this line-size is the same for all CPUs.
753 	status = ia64_pal_cache_config_info(levels - 1,  in set_pci_dfl_cacheline_size()
765 	u32 low_totalram = ((max_pfn - 1) << PAGE_SHIFT);  in ia64_dma_get_required_mask()
766 	u32 high_totalram = ((max_pfn - 1) >> (32 - PAGE_SHIFT));  in ia64_dma_get_required_mask()
771 		low_totalram = (1 << (fls(low_totalram) - 1));  in ia64_dma_get_required_mask()
772 		low_totalram += low_totalram - 1;  in ia64_dma_get_required_mask()
775 		high_totalram = (1 << (fls(high_totalram) - 1));  in ia64_dma_get_required_mask()
776 		high_totalram += high_totalram - 1;  in ia64_dma_get_required_mask()