2  * AMD 76x Memory Controller kernel module
9  *	http://www.anime.net/~goemon/linux-ecc/
35 /* AMD 76x register addresses - device 0 function 0 - PCI bridge */
51 					 * 31:26 clock disable 5 - 0
59 					 * 17:16 cycles-per-refresh
61 					 *  7:0  x4 mode enable 7 - 0
64 #define AMD76X_MEM_BASE_ADDR	0xC0	/* Memory base address (8 x 32b)
66 					 * 31:23 chip-select base
68 					 * 15:7  chip-select mask
71 					 *  0    chip-select enable
97  *	amd76x_get_error_info	-	fetch error information
98  *	@mci: Memory controller
109 	pdev = to_pci_dev(mci->dev);  in amd76x_get_error_info()
111 			&info->ecc_mode_status);  in amd76x_get_error_info()
113 	if (info->ecc_mode_status & BIT(8))  in amd76x_get_error_info()
117 	if (info->ecc_mode_status & BIT(9))  in amd76x_get_error_info()
123  *	amd76x_process_error_info	-	Error check
124  *	@mci: Memory controller
144 	if (info->ecc_mode_status & BIT(8)) {  in amd76x_process_error_info()
148 			row = (info->ecc_mode_status >> 4) & 0xf;  in amd76x_process_error_info()
149 			edac_mc_handle_ue(mci, mci->csrows[row].first_page, 0,  in amd76x_process_error_info()
150 					row, mci->ctl_name);  in amd76x_process_error_info()
157 	if (info->ecc_mode_status & BIT(9)) {  in amd76x_process_error_info()
161 			row = info->ecc_mode_status & 0xf;  in amd76x_process_error_info()
162 			edac_mc_handle_ce(mci, mci->csrows[row].first_page, 0,  in amd76x_process_error_info()
163 					0, row, 0, mci->ctl_name);  in amd76x_process_error_info()
171  *	amd76x_check	-	Poll the controller
172  *	@mci: Memory controller
175  *	from the controller and checks for errors.
192 	for (index = 0; index < mci->nr_csrows; index++) {  in amd76x_init_csrows()
193 		csrow = &mci->csrows[index];  in amd76x_init_csrows()
205 		csrow->first_page = mba_base >> PAGE_SHIFT;  in amd76x_init_csrows()
206 		csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;  in amd76x_init_csrows()
207 		csrow->last_page = csrow->first_page + csrow->nr_pages - 1;  in amd76x_init_csrows()
208 		csrow->page_mask = mba_mask >> PAGE_SHIFT;  in amd76x_init_csrows()
209 		csrow->grain = csrow->nr_pages << PAGE_SHIFT;  in amd76x_init_csrows()
210 		csrow->mtype = MEM_RDDR;  in amd76x_init_csrows()
211 		csrow->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN;  in amd76x_init_csrows()
212 		csrow->edac_mode = edac_mode;  in amd76x_init_csrows()
217  *	amd76x_probe1	-	Perform set up for detected device
221  *	We have found an AMD76x and now need to set up the memory
222  *	controller status reporting. We configure and set up the
223  *	memory controller reporting and claim the device.
244 		return -ENOMEM;  in amd76x_probe1()
248 	mci->dev = &pdev->dev;  in amd76x_probe1()
249 	mci->mtype_cap = MEM_FLAG_RDDR;  in amd76x_probe1()
250 	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;  in amd76x_probe1()
251 	mci->edac_cap = ems_mode ?  in amd76x_probe1()
253 	mci->mod_name = EDAC_MOD_STR;  in amd76x_probe1()
254 	mci->mod_ver = AMD76X_REVISION;  in amd76x_probe1()
255 	mci->ctl_name = amd76x_devs[dev_idx].ctl_name;  in amd76x_probe1()
256 	mci->dev_name = pci_name(pdev);  in amd76x_probe1()
257 	mci->edac_check = amd76x_check;  in amd76x_probe1()
258 	mci->ctl_page_to_phys = NULL;  in amd76x_probe1()
264 	 * type of memory controller.  The ID is therefore hardcoded to 0.  in amd76x_probe1()
272 	amd76x_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);  in amd76x_probe1()
288 	return -ENODEV;  in amd76x_probe1()
298 	return amd76x_probe1(pdev, ent->driver_data);  in amd76x_init_one()
302  *	amd76x_remove_one	-	driver shutdown
318 	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)  in amd76x_remove_one()
363 MODULE_DESCRIPTION("MC support for AMD 76x memory controllers");