38  * -------------------------------
74 	return res->start;  in pcibios_align_resource()
81  * controller_id is the controller number, config type is 0 or 1 for
101 				 struct pci_controller *controller)  in tile_init_irqs()  argument
113 		return -1;  in tile_init_irqs()
121 		return -1;  in tile_init_irqs()
124 	controller->irq_base = rc_config.intr;  in tile_init_irqs()
131 		controller->plx_gen1 = 1;  in tile_init_irqs()
150 	/* Re-init number of PCIe controllers to support hot-plug feature. */  in tile_pci_init()
158 		 * the results of pcibios_init(), to support PCIe hot-plug.  in tile_pci_init()
161 			int hv_cfg_fd0 = -1;  in tile_pci_init()
162 			int hv_cfg_fd1 = -1;  in tile_pci_init()
163 			int hv_mem_fd = -1;  in tile_pci_init()
165 			struct pci_controller *controller;  in tile_pci_init()  local
177 				    "for controller %d\n", i);  in tile_pci_init()
188 			pr_info("PCI: Found PCI controller #%d\n", i);  in tile_pci_init()
190 			controller = &controllers[i];  in tile_pci_init()
192 			controller->index = i;  in tile_pci_init()
193 			controller->hv_cfg_fd[0] = hv_cfg_fd0;  in tile_pci_init()
194 			controller->hv_cfg_fd[1] = hv_cfg_fd1;  in tile_pci_init()
195 			controller->hv_mem_fd = hv_mem_fd;  in tile_pci_init()
196 			controller->first_busno = 0;  in tile_pci_init()
197 			controller->last_busno = 0xff;  in tile_pci_init()
198 			controller->ops = &tile_cfg_ops;  in tile_pci_init()
215 	 * Before using the PCIe, see if we need to do any platform-specific  in tile_pci_init()
219 		struct pci_controller *controller = &controllers[i];  in tile_pci_init()  local
221 		if (controller->plx_gen1)  in tile_pci_init()
229  * (pin - 1) converts from the PCI standard's [1:4] convention to
234 	struct pci_controller *controller =  in tile_map_irq()  local
235 		(struct pci_controller *)dev->sysdata;  in tile_map_irq()
236 	return (pin - 1) + controller->irq_base;  in tile_map_irq()
306 		 * Do real pcibios init ops if the controller is initialized  in pcibios_init()
308 		 * pcibios_init() yet to support PCIe hot-plug.  in pcibios_init()
311 			struct pci_controller *controller = &controllers[i];  in pcibios_init()  local
314 			if (tile_init_irqs(i, controller)) {  in pcibios_init()
319 			pr_info("PCI: initializing controller #%d\n", i);  in pcibios_init()
330 			bus = pci_scan_bus(0, controller->ops, controller);  in pcibios_init()
331 			controller->root_bus = bus;  in pcibios_init()
332 			controller->last_busno = bus->subordinate;  in pcibios_init()
342 	 * It allocates all of the resources (I/O memory, etc)  in pcibios_init()
350 	/* Record the I/O resources in the PCI controller structure. */  in pcibios_init()
353 		 * Do real pcibios init ops if the controller is initialized  in pcibios_init()
355 		 * pcibios_init() yet to support PCIe hot-plug.  in pcibios_init()
362 			list_for_each_entry(dev, &root_bus->devices, bus_list) {  in pcibios_init()
364 				 * Find the PCI host controller, ie. the 1st  in pcibios_init()
367 				if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&  in pcibios_init()
368 					(PCI_SLOT(dev->devfn) == 0)) {  in pcibios_init()
369 					next_bus = dev->subordinate;  in pcibios_init()
371 						*next_bus->resource[0];  in pcibios_init()
373 						 *next_bus->resource[1];  in pcibios_init()
375 						 *next_bus->resource[2];  in pcibios_init()
422  * Enable memory and/or address decoding, as appropriate, for the
441 		 * For bridges, we enable both memory and I/O decoding  in pcibios_enable_device()
448 		 * For endpoints, we enable memory and/or I/O decoding  in pcibios_enable_device()
449 		 * only if they have a memory resource of that type.  in pcibios_enable_device()
452 			r = &dev->resource[i];  in pcibios_enable_device()
453 			if (r->flags & IORESOURCE_UNSET) {  in pcibios_enable_device()
457 				return -EINVAL;  in pcibios_enable_device()
459 			if (r->flags & IORESOURCE_IO)  in pcibios_enable_device()
461 			if (r->flags & IORESOURCE_MEM)  in pcibios_enable_device()
496 	struct pci_controller *controller = bus->sysdata;  in tile_cfg_read()  local
497 	int busnum = bus->number & 0xff;  in tile_cfg_read()
527 	return hv_dev_pread(controller->hv_cfg_fd[config_mode], 0,  in tile_cfg_read()
542 	struct pci_controller *controller = bus->sysdata;  in tile_cfg_write()  local
543 	int busnum = bus->number & 0xff;  in tile_cfg_write()
569 	/* Point to the correct part of the 32-bit "val". */  in tile_cfg_write()
570 	valp += 4 - size;  in tile_cfg_write()
573 	return hv_dev_pwrite(controller->hv_cfg_fd[config_mode], 0,  in tile_cfg_write()
585  * In the following, each PCI controller's mem_resources[1]
586  * represents its (non-prefetchable) PCI memory resource.
588  * prefetchable PCI memory resources, respectively.
589  * For more details, see pci_setup_bridge() in setup-bus.c.
590  * By comparing the target PCI memory address against the
591  * end address of controller 0, we can determine the controller
592  * that should accept the PCI memory access.