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/linux-3.3/Documentation/devicetree/bindings/powerpc/fsl/
Dmsi-pic.txt1 * Freescale MSI interrupt controller
4 - compatible : compatible list, contains 2 entries,
5 first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
6 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
9 - reg : should contain the address and the length of the shared message
12 - msi-available-ranges: use <start count> style section to define which
13 msi interrupt can be used in the 256 msi interrupts. This property is
14 optional, without this, all the 256 MSI interrupts can be used.
16 no splitting an individual MSI register or the associated PIC interrupt).
18 - interrupts : each one of the interrupts here is one entry per 32 MSIs,
[all …]
/linux-3.3/arch/powerpc/sysdev/
Dmsi_bitmap.c2 * Copyright 2006-2008, Michael Ellerman, IBM Corporation.
21 spin_lock_irqsave(&bmp->lock, flags); in msi_bitmap_alloc_hwirqs()
26 offset = bitmap_find_free_region(bmp->bitmap, bmp->irq_count, order); in msi_bitmap_alloc_hwirqs()
27 spin_unlock_irqrestore(&bmp->lock, flags); in msi_bitmap_alloc_hwirqs()
44 spin_lock_irqsave(&bmp->lock, flags); in msi_bitmap_free_hwirqs()
45 bitmap_release_region(bmp->bitmap, offset, order); in msi_bitmap_free_hwirqs()
46 spin_unlock_irqrestore(&bmp->lock, flags); in msi_bitmap_free_hwirqs()
55 spin_lock_irqsave(&bmp->lock, flags); in msi_bitmap_reserve_hwirq()
56 bitmap_allocate_region(bmp->bitmap, hwirq, 0); in msi_bitmap_reserve_hwirq()
57 spin_unlock_irqrestore(&bmp->lock, flags); in msi_bitmap_reserve_hwirq()
[all …]
Dfsl_msi.c2 * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
17 #include <linux/msi.h>
24 #include <asm/ppc-pci.h>
50 * in the cascade interrupt. So, this MSI interrupt has been acked
60 .name = "FSL-MSI",
66 struct fsl_msi *msi_data = h->host_data; in fsl_msi_host_map()
85 rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS, in fsl_msi_init_allocator()
86 msi_data->irqhost->of_node); in fsl_msi_init_allocator()
90 rc = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap); in fsl_msi_init_allocator()
92 msi_bitmap_free(&msi_data->bitmap); in fsl_msi_init_allocator()
[all …]
/linux-3.3/arch/powerpc/boot/dts/fsl/
Dqoriq-mpic.dtsi36 interrupt-controller;
37 #address-cells = <0>;
38 #interrupt-cells = <4>;
40 compatible = "fsl,mpic", "chrp,open-pic";
41 device_type = "open-pic";
42 clock-frequency = <0x0>;
46 compatible = "fsl,mpic-global-timer";
54 msi0: msi@41600 {
55 compatible = "fsl,mpic-msi";
57 msi-available-ranges = <0 0x100>;
[all …]
/linux-3.3/arch/powerpc/boot/dts/
Dp3041ds.dts4 * Copyright 2010-2011 Freescale Semiconductor Inc.
35 /include/ "fsl/p3041si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
49 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
53 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
57 #address-cells = <1>;
58 #size-cells = <1>;
61 spi-max-frequency = <40000000>; /* input clock */
[all …]
Dp5020ds.dts4 * Copyright 2010-2011 Freescale Semiconductor Inc.
35 /include/ "fsl/p5020si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
49 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
53 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
57 #address-cells = <1>;
58 #size-cells = <1>;
61 spi-max-frequency = <40000000>; /* input clock */
[all …]
Dp4080ds.dts4 * Copyright 2009-2011 Freescale Semiconductor Inc.
35 /include/ "fsl/p4080si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
49 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
53 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
58 #address-cells = <1>;
59 #size-cells = <1>;
62 spi-max-frequency = <40000000>; /* input clock */
[all …]
Dp2041rdb.dts35 /include/ "fsl/p2041si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
49 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
53 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
57 #address-cells = <1>;
58 #size-cells = <1>;
61 spi-max-frequency = <40000000>; /* input clock */
62 partition@u-boot {
[all …]
Dredwood.dts11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
26 #address-cells = <1>;
27 #size-cells = <0>;
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */
35 i-cache-line-size = <32>;
36 d-cache-line-size = <32>;
[all …]
Dkatmai.dts15 /dts-v1/;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 dcr-parent = <&{/cpus/cpu@0}>;
32 #address-cells = <1>;
33 #size-cells = <0>;
39 clock-frequency = <0>; /* Filled in by zImage */
40 timebase-frequency = <0>; /* Filled in by zImage */
41 i-cache-line-size = <32>;
42 d-cache-line-size = <32>;
[all …]
Dcanyonlands.dts4 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
[all …]
Dkilauea.dts4 * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
[all …]
Dgef_sbc310.dts18 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
21 /dts-v1/;
26 #address-cells = <1>;
27 #size-cells = <1>;
39 #address-cells = <1>;
40 #size-cells = <0>;
45 d-cache-line-size = <32>; // 32 bytes
46 i-cache-line-size = <32>; // 32 bytes
47 d-cache-size = <32768>; // L1, 32K
48 i-cache-size = <32768>; // L1, 32K
[all …]
Dgef_sbc610.dts18 * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
21 /dts-v1/;
26 #address-cells = <1>;
27 #size-cells = <1>;
38 #address-cells = <1>;
39 #size-cells = <0>;
44 d-cache-line-size = <32>; // 32 bytes
45 i-cache-line-size = <32>; // 32 bytes
46 d-cache-size = <32768>; // L1, 32K
47 i-cache-size = <32768>; // L1, 32K
[all …]
Dmpc8610_hpcd.dts4 * Copyright 2007-2008 Freescale Semiconductor Inc.
11 /dts-v1/;
16 #address-cells = <1>;
17 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <32768>; // L1
37 i-cache-size = <32768>; // L1
[all …]
Dmpc8308rdb.dts13 /dts-v1/;
17 #address-cells = <1>;
18 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 d-cache-line-size = <32>;
36 i-cache-line-size = <32>;
37 d-cache-size = <16384>;
38 i-cache-size = <16384>;
39 timebase-frequency = <0>; // from bootloader
[all …]
Dp3060qds.dts35 /include/ "fsl/p3060si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
49 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
53 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
57 #address-cells = <1>;
58 #size-cells = <1>;
61 spi-max-frequency = <40000000>; /* input clock */
62 partition@u-boot {
[all …]
Dgef_ppc9a.dts18 * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
21 /dts-v1/;
26 #address-cells = <1>;
27 #size-cells = <1>;
38 #address-cells = <1>;
39 #size-cells = <0>;
44 d-cache-line-size = <32>; // 32 bytes
45 i-cache-line-size = <32>; // 32 bytes
46 d-cache-size = <32768>; // L1, 32K
47 i-cache-size = <32768>; // L1, 32K
[all …]
Dmpc8308_p1m.dts12 /dts-v1/;
16 #address-cells = <1>;
17 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <16384>;
37 i-cache-size = <16384>;
38 timebase-frequency = <0>; // from bootloader
[all …]
Dmpc8572ds_camp_core1.dts6 * This dts allows core1 to have l2, dma2, eth2, eth3, pci2, msi.
8 * Please note to add "-b 1" for core1's dts compiling.
10 * Copyright 2007-2009 Freescale Semiconductor Inc.
22 compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
37 ecm-law@0 {
43 memory-controller@2000 {
46 memory-controller@6000 {
58 gpio-controller@f000 {
61 l2-cache-controller@20000 {
62 cache-size = <0x80000>; // L2, 512K
[all …]
Dmpc8572ds_camp_core0.dts6 * This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0,
9 * Copyright 2007-2009 Freescale Semiconductor Inc.
21 compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
42 gpio-controller@f000 {
44 l2-cache-controller@20000 {
45 cache-size = <0x80000>; // L2, 512K
60 protected-sources = <
63 0xe4 0xe5 0xe6 0xe7 /* msi */
67 msi@41600 {
68 msi-available-ranges = <0 0x80>;
Dmpc8315erdb.dts12 /dts-v1/;
16 #address-cells = <1>;
17 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
36 d-cache-line-size = <32>;
37 i-cache-line-size = <32>;
38 d-cache-size = <16384>;
39 i-cache-size = <16384>;
40 timebase-frequency = <0>; // from bootloader
[all …]
Dxpedite5301.dts12 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <2>;
18 form-factor = "PMC/XMC";
19 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
31 #address-cells = <1>;
32 #size-cells = <0>;
37 d-cache-line-size = <32>; // 32 bytes
38 i-cache-line-size = <32>; // 32 bytes
39 d-cache-size = <0x8000>; // L1, 32K
[all …]
Dxpedite5370.dts5 * XPedite5370 3U VPX single-board computer based on MPC8572E
12 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <2>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
[all …]
/linux-3.3/arch/sparc/kernel/
Dpci_msi.c1 /* pci_msi.c: Sparc64 MSI support common layer.
15 struct pci_pbm_info *pbm = msiq_cookie->pbm; in sparc64_msiq_interrupt()
16 unsigned long msiqid = msiq_cookie->msiqid; in sparc64_msiq_interrupt()
21 ops = pbm->msi_ops; in sparc64_msiq_interrupt()
23 err = ops->get_head(pbm, msiqid, &head); in sparc64_msiq_interrupt()
29 unsigned long msi; in sparc64_msiq_interrupt() local
31 err = ops->dequeue_msi(pbm, msiqid, &head, &msi); in sparc64_msiq_interrupt()
35 irq = pbm->msi_irq_table[msi - pbm->msi_first]; in sparc64_msiq_interrupt()
46 err = ops->set_head(pbm, msiqid, head); in sparc64_msiq_interrupt()
53 printk(KERN_EMERG "MSI: Get head on msiqid[%lu] gives error %d\n", in sparc64_msiq_interrupt()
[all …]

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