Lines Matching +full:msi +full:- +full:ranges
4 * Copyright 2009-2011 Freescale Semiconductor Inc.
35 /include/ "fsl/p4080si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
49 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
53 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
58 #address-cells = <1>;
59 #size-cells = <1>;
62 spi-max-frequency = <40000000>; /* input clock */
63 partition@u-boot {
64 label = "u-boot";
66 read-only;
71 read-only;
76 read-only;
115 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
118 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
124 ranges = <0 0 0xf 0xe8000000 0x08000000
128 compatible = "cfi-flash";
130 bank-width = <2>;
131 device-width = <2>;
134 board-control@3,0 {
135 compatible = "fsl,p4080ds-fpga", "fsl,fpga-ngpixis";
142 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
144 fsl,msi = <&msi0>;
146 ranges = <0x02000000 0 0xe0000000
158 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
160 fsl,msi = <&msi1>;
162 ranges = <0x02000000 0 0xe0000000
174 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
176 fsl,msi = <&msi2>;
178 ranges = <0x02000000 0 0xe0000000
190 /include/ "fsl/p4080si-post.dtsi"