Lines Matching +full:msi +full:- +full:ranges
5 * XPedite5370 3U VPX single-board computer based on MPC8572E
12 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <2>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>;
40 bus-frequency = <0>;
41 clock-frequency = <0>;
42 next-level-cache = <&L2>;
48 d-cache-line-size = <32>; // 32 bytes
49 i-cache-line-size = <32>; // 32 bytes
50 d-cache-size = <0x8000>; // L1, 32K
51 i-cache-size = <0x8000>; // L1, 32K
52 timebase-frequency = <0>;
53 bus-frequency = <0>;
54 clock-frequency = <0>;
55 next-level-cache = <&L2>;
61 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
65 #address-cells = <2>;
66 #size-cells = <1>;
67 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
70 interrupt-parent = <&mpic>;
72 ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
77 nor-boot@0,0 {
78 compatible = "amd,s29gl01gp", "cfi-flash";
79 bank-width = <2>;
81 #address-cells = <1>;
82 #size-cells = <1>;
96 label = "Primary U-Boot environment";
100 label = "Primary U-Boot";
102 read-only;
106 nor-alternate@1,0 {
107 compatible = "amd,s29gl01gp", "cfi-flash";
108 bank-width = <2>;
111 #address-cells = <1>;
112 #size-cells = <1>;
126 label = "Secondary U-Boot environment";
130 label = "Secondary U-Boot";
132 read-only;
137 #address-cells = <1>;
138 #size-cells = <1>;
145 compatible = "fsl,mpc8572-fcm-nand",
146 "fsl,elbc-fcm-nand";
148 /* U-Boot should fix this up if chip size > 1 GB */
158 #address-cells = <1>;
159 #size-cells = <1>;
161 compatible = "fsl,mpc8572-immr", "simple-bus";
162 ranges = <0x0 0 0xef000000 0x100000>;
163 bus-frequency = <0>; // Filled out by uboot.
165 ecm-law@0 {
166 compatible = "fsl,ecm-law";
168 fsl,num-laws = <12>;
172 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
175 interrupt-parent = <&mpic>;
178 memory-controller@2000 {
179 compatible = "fsl,mpc8572-memory-controller";
181 interrupt-parent = <&mpic>;
185 memory-controller@6000 {
186 compatible = "fsl,mpc8572-memory-controller";
188 interrupt-parent = <&mpic>;
192 L2: l2-cache-controller@20000 {
193 compatible = "fsl,mpc8572-l2-cache-controller";
195 cache-line-size = <32>; // 32 bytes
196 cache-size = <0x100000>; // L2, 1M
197 interrupt-parent = <&mpic>;
202 #address-cells = <1>;
203 #size-cells = <0>;
204 cell-index = <0>;
205 compatible = "fsl-i2c";
208 interrupt-parent = <&mpic>;
211 temp-sensor@48 {
216 temp-sensor@4c {
221 cpu-supervisor@51 {
237 pcie-switch@70 {
245 #gpio-cells = <2>;
246 gpio-controller;
253 #gpio-cells = <2>;
254 gpio-controller;
261 #gpio-cells = <2>;
262 gpio-controller;
269 #gpio-cells = <2>;
270 gpio-controller;
276 #address-cells = <1>;
277 #size-cells = <0>;
278 cell-index = <1>;
279 compatible = "fsl-i2c";
282 interrupt-parent = <&mpic>;
287 #address-cells = <1>;
288 #size-cells = <1>;
289 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
291 ranges = <0x0 0xc100 0x200>;
292 cell-index = <1>;
293 dma-channel@0 {
294 compatible = "fsl,mpc8572-dma-channel",
295 "fsl,eloplus-dma-channel";
297 cell-index = <0>;
298 interrupt-parent = <&mpic>;
301 dma-channel@80 {
302 compatible = "fsl,mpc8572-dma-channel",
303 "fsl,eloplus-dma-channel";
305 cell-index = <1>;
306 interrupt-parent = <&mpic>;
309 dma-channel@100 {
310 compatible = "fsl,mpc8572-dma-channel",
311 "fsl,eloplus-dma-channel";
313 cell-index = <2>;
314 interrupt-parent = <&mpic>;
317 dma-channel@180 {
318 compatible = "fsl,mpc8572-dma-channel",
319 "fsl,eloplus-dma-channel";
321 cell-index = <3>;
322 interrupt-parent = <&mpic>;
328 #address-cells = <1>;
329 #size-cells = <1>;
330 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
332 ranges = <0x0 0x21100 0x200>;
333 cell-index = <0>;
334 dma-channel@0 {
335 compatible = "fsl,mpc8572-dma-channel",
336 "fsl,eloplus-dma-channel";
338 cell-index = <0>;
339 interrupt-parent = <&mpic>;
342 dma-channel@80 {
343 compatible = "fsl,mpc8572-dma-channel",
344 "fsl,eloplus-dma-channel";
346 cell-index = <1>;
347 interrupt-parent = <&mpic>;
350 dma-channel@100 {
351 compatible = "fsl,mpc8572-dma-channel",
352 "fsl,eloplus-dma-channel";
354 cell-index = <2>;
355 interrupt-parent = <&mpic>;
358 dma-channel@180 {
359 compatible = "fsl,mpc8572-dma-channel",
360 "fsl,eloplus-dma-channel";
362 cell-index = <3>;
363 interrupt-parent = <&mpic>;
370 #address-cells = <1>;
371 #size-cells = <1>;
372 cell-index = <0>;
377 ranges = <0x0 0x24000 0x1000>;
378 local-mac-address = [ 00 00 00 00 00 00 ];
380 interrupt-parent = <&mpic>;
381 tbi-handle = <&tbi0>;
382 phy-handle = <&phy0>;
383 phy-connection-type = "sgmii";
386 #address-cells = <1>;
387 #size-cells = <0>;
388 compatible = "fsl,gianfar-mdio";
391 phy0: ethernet-phy@1 {
392 interrupt-parent = <&mpic>;
396 phy1: ethernet-phy@2 {
397 interrupt-parent = <&mpic>;
401 tbi0: tbi-phy@11 {
403 device_type = "tbi-phy";
410 #address-cells = <1>;
411 #size-cells = <1>;
412 cell-index = <1>;
417 ranges = <0x0 0x25000 0x1000>;
418 local-mac-address = [ 00 00 00 00 00 00 ];
420 interrupt-parent = <&mpic>;
421 tbi-handle = <&tbi1>;
422 phy-handle = <&phy1>;
423 phy-connection-type = "sgmii";
426 #address-cells = <1>;
427 #size-cells = <0>;
428 compatible = "fsl,gianfar-tbi";
431 tbi1: tbi-phy@11 {
433 device_type = "tbi-phy";
440 cell-index = <0>;
444 clock-frequency = <0>;
446 interrupt-parent = <&mpic>;
451 cell-index = <1>;
455 clock-frequency = <0>;
457 interrupt-parent = <&mpic>;
460 global-utilities@e0000 { //global utilities block
461 compatible = "fsl,mpc8572-guts";
463 fsl,has-rstcr;
466 msi@41600 {
467 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
469 msi-available-ranges = <0 0x100>;
479 interrupt-parent = <&mpic>;
487 interrupt-parent = <&mpic>;
488 fsl,num-channels = <4>;
489 fsl,channel-fifo-len = <24>;
490 fsl,exec-units-mask = <0x9fe>;
491 fsl,descriptor-types-mask = <0x3ab0ebf>;
495 interrupt-controller;
496 #address-cells = <0>;
497 #interrupt-cells = <2>;
499 compatible = "chrp,open-pic";
500 device_type = "open-pic";
504 compatible = "fsl,mpc8572-gpio";
507 interrupt-parent = <&mpic>;
508 #gpio-cells = <2>;
509 gpio-controller;
512 gpio-leds {
513 compatible = "gpio-leds";
518 linux,default-trigger = "heartbeat";
537 /* PME (pattern-matcher) */
539 compatible = "fsl,mpc8572-pme", "pme8572";
542 interrupt-parent = <&mpic>;
546 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
549 interrupt-parent = <&mpic>;
553 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
556 interrupt-parent = <&mpic>;
567 compatible = "fsl,mpc8548-pcie";
569 #interrupt-cells = <1>;
570 #size-cells = <2>;
571 #address-cells = <3>;
573 bus-range = <0 255>;
574 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
576 clock-frequency = <33333333>;
577 interrupt-parent = <&mpic>;
579 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
580 interrupt-map = <
589 #size-cells = <2>;
590 #address-cells = <3>;
592 ranges = <0x2000000 0x0 0xc0000000
604 compatible = "fsl,mpc8548-pcie";
606 #interrupt-cells = <1>;
607 #size-cells = <2>;
608 #address-cells = <3>;
610 bus-range = <0 255>;
611 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
613 clock-frequency = <33333333>;
614 interrupt-parent = <&mpic>;
616 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
617 interrupt-map = <
626 #size-cells = <2>;
627 #address-cells = <3>;
629 ranges = <0x2000000 0x0 0x80000000