Lines Matching +full:msi +full:- +full:ranges
12 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <2>;
18 form-factor = "PMC/XMC";
19 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
31 #address-cells = <1>;
32 #size-cells = <0>;
37 d-cache-line-size = <32>; // 32 bytes
38 i-cache-line-size = <32>; // 32 bytes
39 d-cache-size = <0x8000>; // L1, 32K
40 i-cache-size = <0x8000>; // L1, 32K
41 timebase-frequency = <0>;
42 bus-frequency = <0>;
43 clock-frequency = <0>;
44 next-level-cache = <&L2>;
50 d-cache-line-size = <32>; // 32 bytes
51 i-cache-line-size = <32>; // 32 bytes
52 d-cache-size = <0x8000>; // L1, 32K
53 i-cache-size = <0x8000>; // L1, 32K
54 timebase-frequency = <0>;
55 bus-frequency = <0>;
56 clock-frequency = <0>;
57 next-level-cache = <&L2>;
63 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
67 #address-cells = <2>;
68 #size-cells = <1>;
69 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
72 interrupt-parent = <&mpic>;
74 ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
79 nor-boot@0,0 {
80 compatible = "amd,s29gl01gp", "cfi-flash";
81 bank-width = <2>;
83 #address-cells = <1>;
84 #size-cells = <1>;
98 label = "Primary U-Boot environment";
102 label = "Primary U-Boot";
104 read-only;
108 nor-alternate@1,0 {
109 compatible = "amd,s29gl01gp", "cfi-flash";
110 bank-width = <2>;
113 #address-cells = <1>;
114 #size-cells = <1>;
128 label = "Secondary U-Boot environment";
132 label = "Secondary U-Boot";
134 read-only;
139 #address-cells = <1>;
140 #size-cells = <1>;
147 compatible = "fsl,mpc8572-fcm-nand",
148 "fsl,elbc-fcm-nand";
150 /* U-Boot should fix this up if chip size > 1 GB */
160 #address-cells = <1>;
161 #size-cells = <1>;
163 compatible = "fsl,mpc8572-immr", "simple-bus";
164 ranges = <0x0 0 0xef000000 0x100000>;
165 bus-frequency = <0>; // Filled out by uboot.
167 ecm-law@0 {
168 compatible = "fsl,ecm-law";
170 fsl,num-laws = <12>;
174 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
177 interrupt-parent = <&mpic>;
180 memory-controller@2000 {
181 compatible = "fsl,mpc8572-memory-controller";
183 interrupt-parent = <&mpic>;
187 memory-controller@6000 {
188 compatible = "fsl,mpc8572-memory-controller";
190 interrupt-parent = <&mpic>;
194 L2: l2-cache-controller@20000 {
195 compatible = "fsl,mpc8572-l2-cache-controller";
197 cache-line-size = <32>; // 32 bytes
198 cache-size = <0x100000>; // L2, 1M
199 interrupt-parent = <&mpic>;
204 #address-cells = <1>;
205 #size-cells = <0>;
206 cell-index = <0>;
207 compatible = "fsl-i2c";
210 interrupt-parent = <&mpic>;
213 temp-sensor@48 {
218 temp-sensor@4c {
223 cpu-supervisor@51 {
239 pcie-switch@70 {
247 #gpio-cells = <2>;
248 gpio-controller;
255 #gpio-cells = <2>;
256 gpio-controller;
263 #gpio-cells = <2>;
264 gpio-controller;
271 #gpio-cells = <2>;
272 gpio-controller;
278 #address-cells = <1>;
279 #size-cells = <0>;
280 cell-index = <1>;
281 compatible = "fsl-i2c";
284 interrupt-parent = <&mpic>;
289 #address-cells = <1>;
290 #size-cells = <1>;
291 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
293 ranges = <0x0 0xc100 0x200>;
294 cell-index = <1>;
295 dma-channel@0 {
296 compatible = "fsl,mpc8572-dma-channel",
297 "fsl,eloplus-dma-channel";
299 cell-index = <0>;
300 interrupt-parent = <&mpic>;
303 dma-channel@80 {
304 compatible = "fsl,mpc8572-dma-channel",
305 "fsl,eloplus-dma-channel";
307 cell-index = <1>;
308 interrupt-parent = <&mpic>;
311 dma-channel@100 {
312 compatible = "fsl,mpc8572-dma-channel",
313 "fsl,eloplus-dma-channel";
315 cell-index = <2>;
316 interrupt-parent = <&mpic>;
319 dma-channel@180 {
320 compatible = "fsl,mpc8572-dma-channel",
321 "fsl,eloplus-dma-channel";
323 cell-index = <3>;
324 interrupt-parent = <&mpic>;
330 #address-cells = <1>;
331 #size-cells = <1>;
332 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
334 ranges = <0x0 0x21100 0x200>;
335 cell-index = <0>;
336 dma-channel@0 {
337 compatible = "fsl,mpc8572-dma-channel",
338 "fsl,eloplus-dma-channel";
340 cell-index = <0>;
341 interrupt-parent = <&mpic>;
344 dma-channel@80 {
345 compatible = "fsl,mpc8572-dma-channel",
346 "fsl,eloplus-dma-channel";
348 cell-index = <1>;
349 interrupt-parent = <&mpic>;
352 dma-channel@100 {
353 compatible = "fsl,mpc8572-dma-channel",
354 "fsl,eloplus-dma-channel";
356 cell-index = <2>;
357 interrupt-parent = <&mpic>;
360 dma-channel@180 {
361 compatible = "fsl,mpc8572-dma-channel",
362 "fsl,eloplus-dma-channel";
364 cell-index = <3>;
365 interrupt-parent = <&mpic>;
372 #address-cells = <1>;
373 #size-cells = <1>;
374 cell-index = <0>;
379 ranges = <0x0 0x24000 0x1000>;
380 local-mac-address = [ 00 00 00 00 00 00 ];
382 interrupt-parent = <&mpic>;
383 tbi-handle = <&tbi0>;
384 phy-handle = <&phy0>;
385 phy-connection-type = "sgmii";
388 #address-cells = <1>;
389 #size-cells = <0>;
390 compatible = "fsl,gianfar-mdio";
393 phy0: ethernet-phy@1 {
394 interrupt-parent = <&mpic>;
398 phy1: ethernet-phy@2 {
399 interrupt-parent = <&mpic>;
403 tbi0: tbi-phy@11 {
405 device_type = "tbi-phy";
412 #address-cells = <1>;
413 #size-cells = <1>;
414 cell-index = <1>;
419 ranges = <0x0 0x25000 0x1000>;
420 local-mac-address = [ 00 00 00 00 00 00 ];
422 interrupt-parent = <&mpic>;
423 tbi-handle = <&tbi1>;
424 phy-handle = <&phy1>;
425 phy-connection-type = "sgmii";
428 #address-cells = <1>;
429 #size-cells = <0>;
430 compatible = "fsl,gianfar-tbi";
433 tbi1: tbi-phy@11 {
435 device_type = "tbi-phy";
442 cell-index = <0>;
446 clock-frequency = <0>;
448 interrupt-parent = <&mpic>;
453 cell-index = <1>;
457 clock-frequency = <0>;
459 interrupt-parent = <&mpic>;
462 global-utilities@e0000 { //global utilities block
463 compatible = "fsl,mpc8572-guts";
465 fsl,has-rstcr;
468 msi@41600 {
469 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
471 msi-available-ranges = <0 0x100>;
481 interrupt-parent = <&mpic>;
489 interrupt-parent = <&mpic>;
490 fsl,num-channels = <4>;
491 fsl,channel-fifo-len = <24>;
492 fsl,exec-units-mask = <0x9fe>;
493 fsl,descriptor-types-mask = <0x3ab0ebf>;
497 interrupt-controller;
498 #address-cells = <0>;
499 #interrupt-cells = <2>;
501 compatible = "chrp,open-pic";
502 device_type = "open-pic";
506 compatible = "fsl,mpc8572-gpio";
509 interrupt-parent = <&mpic>;
510 #gpio-cells = <2>;
511 gpio-controller;
514 gpio-leds {
515 compatible = "gpio-leds";
520 linux,default-trigger = "heartbeat";
539 /* PME (pattern-matcher) */
541 compatible = "fsl,mpc8572-pme", "pme8572";
544 interrupt-parent = <&mpic>;
548 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
551 interrupt-parent = <&mpic>;
555 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
558 interrupt-parent = <&mpic>;
569 compatible = "fsl,mpc8548-pcie";
571 #interrupt-cells = <1>;
572 #size-cells = <2>;
573 #address-cells = <3>;
575 bus-range = <0 255>;
576 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
578 clock-frequency = <33333333>;
579 interrupt-parent = <&mpic>;
581 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
582 interrupt-map = <
591 #size-cells = <2>;
592 #address-cells = <3>;
594 ranges = <0x2000000 0x0 0xc0000000
606 compatible = "fsl,mpc8548-pcie";
608 #interrupt-cells = <1>;
609 #size-cells = <2>;
610 #address-cells = <3>;
612 bus-range = <0 255>;
613 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
615 clock-frequency = <33333333>;
616 interrupt-parent = <&mpic>;
618 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
619 interrupt-map = <
628 #size-cells = <2>;
629 #address-cells = <3>;
631 ranges = <0x2000000 0x0 0x80000000