boot/dts/gef_sbc610.dts

18  * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
21 /dts-v1/;
26 	#address-cells = <1>;
27 	#size-cells = <1>;
38 		#address-cells = <1>;
39 		#size-cells = <0>;
44 			d-cache-line-size = <32>;	// 32 bytes
45 			i-cache-line-size = <32>;	// 32 bytes
46 			d-cache-size = <32768>;		// L1, 32K
47 			i-cache-size = <32768>;		// L1, 32K
48 			timebase-frequency = <0>;	// From uboot
49 			bus-frequency = <0>;		// From uboot
50 			clock-frequency = <0>;		// From uboot
55 			d-cache-line-size = <32>;	// 32 bytes
56 			i-cache-line-size = <32>;	// 32 bytes
57 			d-cache-size = <32768>;		// L1, 32K
58 			i-cache-size = <32768>;		// L1, 32K
59 			timebase-frequency = <0>;	// From uboot
60 			bus-frequency = <0>;		// From uboot
61 			clock-frequency = <0>;		// From uboot
71 		#address-cells = <2>;
72 		#size-cells = <1>;
73 		compatible = "fsl,mpc8641-localbus", "simple-bus";
76 		interrupt-parent = <&mpic>;
78 		ranges = <0 0 0xff000000 0x01000000	// 16MB Boot flash
84 			  6 0 0xfd000000 0x00800000	// IO FPGA (8-bit)
85 			  7 0 0xfd800000 0x00800000>;	// IO FPGA (32-bit)
89 			compatible = "gef,sbc610-firmware-mirror", "cfi-flash";
91 			bank-width = <4>;
92 			device-width = <2>;
93 			#address-cells = <1>;
94 			#size-cells = <1>;
98 				read-only;
104 			compatible = "gef,sbc610-paged-flash", "cfi-flash";
106 			bank-width = <4>;
107 			device-width = <2>;
108 			#address-cells = <1>;
109 			#size-cells = <1>;
117 				read-only;
128 			compatible = "gef,fpga-regs";
133 			compatible = "gef,fpga-wdt";
136 			interrupt-parent = <&gef_pic>;
140 			compatible = "gef,fpga-wdt";
143 			interrupt-parent = <&gef_pic>;
147 			#interrupt-cells = <1>;
148 			interrupt-controller;
149 			compatible = "gef,fpga-pic";
153 			interrupt-parent = <&mpic>;
157 			#gpio-cells = <2>;
158 			compatible = "gef,sbc610-gpio";
160 			gpio-controller;
165 		#address-cells = <1>;
166 		#size-cells = <1>;
167 		#interrupt-cells = <2>;
169 		compatible = "simple-bus";
170 		ranges = <0x0 0xfef00000 0x00100000>;
171 		bus-frequency = <33333333>;
173 		mcm-law@0 {
174 			compatible = "fsl,mcm-law";
176 			fsl,num-laws = <10>;
180 			compatible = "fsl,mpc8641-mcm", "fsl,mcm";
183 			interrupt-parent = <&mpic>;
187 			#address-cells = <1>;
188 			#size-cells = <0>;
189 			compatible = "fsl-i2c";
192 			interrupt-parent = <&mpic>;
217 			#address-cells = <1>;
218 			#size-cells = <0>;
219 			compatible = "fsl-i2c";
222 			interrupt-parent = <&mpic>;
227 			#address-cells = <1>;
228 			#size-cells = <1>;
229 			compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
231 			ranges = <0x0 0x21100 0x200>;
232 			cell-index = <0>;
233 			dma-channel@0 {
234 				compatible = "fsl,mpc8641-dma-channel",
235 					   "fsl,eloplus-dma-channel";
237 				cell-index = <0>;
238 				interrupt-parent = <&mpic>;
241 			dma-channel@80 {
242 				compatible = "fsl,mpc8641-dma-channel",
243 					   "fsl,eloplus-dma-channel";
245 				cell-index = <1>;
246 				interrupt-parent = <&mpic>;
249 			dma-channel@100 {
250 				compatible = "fsl,mpc8641-dma-channel",
251 					   "fsl,eloplus-dma-channel";
253 				cell-index = <2>;
254 				interrupt-parent = <&mpic>;
257 			dma-channel@180 {
258 				compatible = "fsl,mpc8641-dma-channel",
259 					   "fsl,eloplus-dma-channel";
261 				cell-index = <3>;
262 				interrupt-parent = <&mpic>;
268 			#address-cells = <1>;
269 			#size-cells = <1>;
270 			cell-index = <0>;
275 			ranges = <0x0 0x24000 0x1000>;
276 			local-mac-address = [ 00 00 00 00 00 00 ];
278 			interrupt-parent = <&mpic>;
279 			tbi-handle = <&tbi0>;
280 			phy-handle = <&phy0>;
281 			phy-connection-type = "gmii";
284 				#address-cells = <1>;
285 				#size-cells = <0>;
286 				compatible = "fsl,gianfar-mdio";
289 				phy0: ethernet-phy@0 {
290 					interrupt-parent = <&gef_pic>;
293 					device_type = "ethernet-phy";
295 				phy2: ethernet-phy@2 {
296 					interrupt-parent = <&gef_pic>;
299 					device_type = "ethernet-phy";
301 				tbi0: tbi-phy@11 {
303 					device_type = "tbi-phy";
309 			#address-cells = <1>;
310 			#size-cells = <1>;
311 			cell-index = <2>;
316 			ranges = <0x0 0x26000 0x1000>;
317 			local-mac-address = [ 00 00 00 00 00 00 ];
319 			interrupt-parent = <&mpic>;
320 			tbi-handle = <&tbi2>;
321 			phy-handle = <&phy2>;
322 			phy-connection-type = "gmii";
325 				#address-cells = <1>;
326 				#size-cells = <0>;
327 				compatible = "fsl,gianfar-tbi";
330 				tbi2: tbi-phy@11 {
332 					device_type = "tbi-phy";
338 			cell-index = <0>;
342 			clock-frequency = <0>;
344 			interrupt-parent = <&mpic>;
348 			cell-index = <1>;
352 			clock-frequency = <0>;
354 			interrupt-parent = <&mpic>;
358 			clock-frequency = <0>;
359 			interrupt-controller;
360 			#address-cells = <0>;
361 			#interrupt-cells = <2>;
363 			compatible = "chrp,open-pic";
364 			device_type = "open-pic";
367 		msi@41600 {
368 			compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
370 			msi-available-ranges = <0 0x100>;
380 			interrupt-parent = <&mpic>;
383 		global-utilities@e0000 {
384 			compatible = "fsl,mpc8641-guts";
386 			fsl,has-rstcr;
391 		compatible = "fsl,mpc8641-pcie";
393 		#interrupt-cells = <1>;
394 		#size-cells = <2>;
395 		#address-cells = <3>;
397 		bus-range = <0x0 0xff>;
398 		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
400 		clock-frequency = <33333333>;
401 		interrupt-parent = <&mpic>;
403 		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
404 		interrupt-map = <
413 			#size-cells = <2>;
414 			#address-cells = <3>;
416 			ranges = <0x02000000 0x0 0x80000000