Lines Matching +full:msi +full:- +full:ranges
18 * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
21 /dts-v1/;
26 #address-cells = <1>;
27 #size-cells = <1>;
38 #address-cells = <1>;
39 #size-cells = <0>;
44 d-cache-line-size = <32>; // 32 bytes
45 i-cache-line-size = <32>; // 32 bytes
46 d-cache-size = <32768>; // L1, 32K
47 i-cache-size = <32768>; // L1, 32K
48 timebase-frequency = <0>; // From uboot
49 bus-frequency = <0>; // From uboot
50 clock-frequency = <0>; // From uboot
55 d-cache-line-size = <32>; // 32 bytes
56 i-cache-line-size = <32>; // 32 bytes
57 d-cache-size = <32768>; // L1, 32K
58 i-cache-size = <32768>; // L1, 32K
59 timebase-frequency = <0>; // From uboot
60 bus-frequency = <0>; // From uboot
61 clock-frequency = <0>; // From uboot
71 #address-cells = <2>;
72 #size-cells = <1>;
73 compatible = "fsl,mpc8641-localbus", "simple-bus";
76 interrupt-parent = <&mpic>;
78 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
84 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
85 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
89 compatible = "gef,ppc9a-firmware-mirror", "cfi-flash";
91 bank-width = <4>;
92 device-width = <2>;
93 #address-cells = <1>;
94 #size-cells = <1>;
98 read-only;
104 compatible = "gef,ppc9a-paged-flash", "cfi-flash";
106 bank-width = <4>;
107 device-width = <2>;
108 #address-cells = <1>;
109 #size-cells = <1>;
117 read-only;
128 compatible = "gef,ppc9a-fpga-regs";
133 compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
134 "gef,fpga-wdt";
137 interrupt-parent = <&gef_pic>;
141 compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
142 "gef,fpga-wdt";
145 interrupt-parent = <&gef_pic>;
149 #interrupt-cells = <1>;
150 interrupt-controller;
151 compatible = "gef,ppc9a-fpga-pic", "gef,fpga-pic-1.00";
155 interrupt-parent = <&mpic>;
159 #gpio-cells = <2>;
160 compatible = "gef,ppc9a-gpio", "gef,sbc610-gpio";
162 gpio-controller;
167 #address-cells = <1>;
168 #size-cells = <1>;
169 #interrupt-cells = <2>;
171 compatible = "fsl,mpc8641-soc", "simple-bus";
172 ranges = <0x0 0xfef00000 0x00100000>;
173 bus-frequency = <33333333>;
175 mcm-law@0 {
176 compatible = "fsl,mcm-law";
178 fsl,num-laws = <10>;
182 compatible = "fsl,mpc8641-mcm", "fsl,mcm";
185 interrupt-parent = <&mpic>;
189 #address-cells = <1>;
190 #size-cells = <0>;
191 compatible = "fsl-i2c";
194 interrupt-parent = <&mpic>;
219 #address-cells = <1>;
220 #size-cells = <0>;
221 compatible = "fsl-i2c";
224 interrupt-parent = <&mpic>;
229 #address-cells = <1>;
230 #size-cells = <1>;
231 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
233 ranges = <0x0 0x21100 0x200>;
234 cell-index = <0>;
235 dma-channel@0 {
236 compatible = "fsl,mpc8641-dma-channel",
237 "fsl,eloplus-dma-channel";
239 cell-index = <0>;
240 interrupt-parent = <&mpic>;
243 dma-channel@80 {
244 compatible = "fsl,mpc8641-dma-channel",
245 "fsl,eloplus-dma-channel";
247 cell-index = <1>;
248 interrupt-parent = <&mpic>;
251 dma-channel@100 {
252 compatible = "fsl,mpc8641-dma-channel",
253 "fsl,eloplus-dma-channel";
255 cell-index = <2>;
256 interrupt-parent = <&mpic>;
259 dma-channel@180 {
260 compatible = "fsl,mpc8641-dma-channel",
261 "fsl,eloplus-dma-channel";
263 cell-index = <3>;
264 interrupt-parent = <&mpic>;
270 #address-cells = <1>;
271 #size-cells = <1>;
272 cell-index = <0>;
277 ranges = <0x0 0x24000 0x1000>;
278 local-mac-address = [ 00 00 00 00 00 00 ];
280 interrupt-parent = <&mpic>;
281 tbi-handle = <&tbi0>;
282 phy-handle = <&phy0>;
283 phy-connection-type = "gmii";
286 #address-cells = <1>;
287 #size-cells = <0>;
288 compatible = "fsl,gianfar-mdio";
291 phy0: ethernet-phy@0 {
292 interrupt-parent = <&gef_pic>;
295 device_type = "ethernet-phy";
297 phy2: ethernet-phy@2 {
298 interrupt-parent = <&gef_pic>;
301 device_type = "ethernet-phy";
303 tbi0: tbi-phy@11 {
305 device_type = "tbi-phy";
311 #address-cells = <1>;
312 #size-cells = <1>;
313 cell-index = <2>;
318 ranges = <0x0 0x26000 0x1000>;
319 local-mac-address = [ 00 00 00 00 00 00 ];
321 interrupt-parent = <&mpic>;
322 tbi-handle = <&tbi2>;
323 phy-handle = <&phy2>;
324 phy-connection-type = "gmii";
327 #address-cells = <1>;
328 #size-cells = <0>;
329 compatible = "fsl,gianfar-tbi";
332 tbi2: tbi-phy@11 {
334 device_type = "tbi-phy";
340 cell-index = <0>;
344 clock-frequency = <0>;
346 interrupt-parent = <&mpic>;
350 cell-index = <1>;
354 clock-frequency = <0>;
356 interrupt-parent = <&mpic>;
360 clock-frequency = <0>;
361 interrupt-controller;
362 #address-cells = <0>;
363 #interrupt-cells = <2>;
365 compatible = "chrp,open-pic";
366 device_type = "open-pic";
369 msi@41600 {
370 compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
372 msi-available-ranges = <0 0x100>;
382 interrupt-parent = <&mpic>;
385 global-utilities@e0000 {
386 compatible = "fsl,mpc8641-guts";
388 fsl,has-rstcr;
393 compatible = "fsl,mpc8641-pcie";
395 #interrupt-cells = <1>;
396 #size-cells = <2>;
397 #address-cells = <3>;
399 bus-range = <0x0 0xff>;
400 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
402 clock-frequency = <33333333>;
403 interrupt-parent = <&mpic>;
405 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
406 interrupt-map = <
415 #size-cells = <2>;
416 #address-cells = <3>;
418 ranges = <0x02000000 0x0 0x80000000