Searched +full:interrupt +full:- +full:parent (Results 1 – 25 of 1012) sorted by relevance
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| /linux-3.3/drivers/of/ |
| D | irq.c | 5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
7 * Copyright (C) 1996-2001 Cort Dougan
17 * device tree to actual irq numbers on an interrupt controller
30 * irq_of_parse_and_map - Parse and map an interrupt into linux virq space
31 * @device: Device node of the device whose interrupt is to be mapped
32 * @index: Index of the interrupt to map
50 * of_irq_find_parent - Given a device node, find its interrupt parent node
53 * Returns a pointer to the interrupt parent node, or NULL if the interrupt
54 * parent could not be determined.
65 parp = of_get_property(child, "interrupt-parent", NULL); in of_irq_find_parent()
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| /linux-3.3/arch/powerpc/boot/dts/ |
| D | mpc5121ads.dts | 12 /dts-v1/;
17 #address-cells = <1>;
18 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <0x20>; // 32 bytes
32 i-cache-line-size = <0x20>; // 32 bytes
33 d-cache-size = <0x8000>; // L1, 32K
34 i-cache-size = <0x8000>; // L1, 32K
35 timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
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| D | mpc8379_rdb.dts | 12 /dts-v1/;
16 #address-cells = <1>;
17 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <32768>;
37 i-cache-size = <32768>;
38 timebase-frequency = <0>;
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| D | socrates.dts | 13 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
36 d-cache-line-size = <32>;
37 i-cache-line-size = <32>;
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
40 timebase-frequency = <0>;
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| D | mpc8349emitx.dts | 2 * MPC8349E-mITX Device Tree Source
12 /dts-v1/;
17 #address-cells = <1>;
18 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
36 d-cache-line-size = <32>;
37 i-cache-line-size = <32>;
38 d-cache-size = <32768>;
39 i-cache-size = <32768>;
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| D | c2k.dts | 15 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
22 coherency-off;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <996000000>; /* 996 MHz */
38 bus-frequency = <166666667>; /* 166.6666 MHz */
39 timebase-frequency = <41666667>; /* 166.6666/4 MHz */
40 i-cache-line-size = <32>;
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| D | mpc8377_wlan.dts | 4 * Copyright 2007-2009 Freescale Semiconductor Inc.
13 /dts-v1/;
17 #address-cells = <1>;
18 #size-cells = <1>;
31 #address-cells = <1>;
32 #size-cells = <0>;
37 d-cache-line-size = <32>;
38 i-cache-line-size = <32>;
39 d-cache-size = <32768>;
40 i-cache-size = <32768>;
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| D | mpc8349emitxgp.dts | 2 * MPC8349E-mITX-GP Device Tree Source
12 /dts-v1/;
17 #address-cells = <1>;
18 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <32768>;
37 i-cache-size = <32768>;
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| D | tqm8555.dts | 12 /dts-v1/;
17 #address-cells = <1>;
18 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 d-cache-line-size = <32>;
36 i-cache-line-size = <32>;
37 d-cache-size = <32768>;
38 i-cache-size = <32768>;
39 timebase-frequency = <0>;
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| D | tqm8541.dts | 12 /dts-v1/;
17 #address-cells = <1>;
18 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 d-cache-line-size = <32>;
36 i-cache-line-size = <32>;
37 d-cache-size = <32768>;
38 i-cache-size = <32768>;
39 timebase-frequency = <0>;
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| D | mpc8379_mds.dts | 12 /dts-v1/;
17 #address-cells = <1>;
18 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 d-cache-line-size = <32>;
36 i-cache-line-size = <32>;
37 d-cache-size = <32768>;
38 i-cache-size = <32768>;
39 timebase-frequency = <0>;
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| D | tqm8560.dts | 13 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
31 #address-cells = <1>;
32 #size-cells = <0>;
37 d-cache-line-size = <32>;
38 i-cache-line-size = <32>;
39 d-cache-size = <32768>;
40 i-cache-size = <32768>;
41 timebase-frequency = <0>;
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| D | sbc8560.dts | 14 /dts-v1/;
19 #address-cells = <1>;
20 #size-cells = <1>;
33 #address-cells = <1>;
34 #size-cells = <0>;
39 d-cache-line-size = <0x20>; // 32 bytes
40 i-cache-line-size = <0x20>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
43 timebase-frequency = <0>; // From uboot
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| D | mpc8315erdb.dts | 12 /dts-v1/;
16 #address-cells = <1>;
17 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
36 d-cache-line-size = <32>;
37 i-cache-line-size = <32>;
38 d-cache-size = <16384>;
39 i-cache-size = <16384>;
40 timebase-frequency = <0>; // from bootloader
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| D | tqm8540.dts | 12 /dts-v1/;
17 #address-cells = <1>;
18 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
36 d-cache-line-size = <32>;
37 i-cache-line-size = <32>;
38 d-cache-size = <32768>;
39 i-cache-size = <32768>;
40 timebase-frequency = <0>;
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| D | sbc8349.dts | 8 * -based largely on the Freescale MPC834x_MDS dts.
16 /dts-v1/;
21 #address-cells = <1>;
22 #size-cells = <1>;
33 #address-cells = <1>;
34 #size-cells = <0>;
39 d-cache-line-size = <32>;
40 i-cache-line-size = <32>;
41 d-cache-size = <32768>;
42 i-cache-size = <32768>;
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| D | asp834x-redboot.dts | 12 /dts-v1/;
16 compatible = "analogue-and-micro,asp8347e";
17 #address-cells = <1>;
18 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <32768>;
37 i-cache-size = <32768>;
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| D | mpc8313erdb.dts | 12 /dts-v1/;
17 #address-cells = <1>;
18 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 d-cache-line-size = <32>;
36 i-cache-line-size = <32>;
37 d-cache-size = <16384>;
38 i-cache-size = <16384>;
39 timebase-frequency = <0>; // from bootloader
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| D | tqm8548-bigflash.dts | 13 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
34 #address-cells = <1>;
35 #size-cells = <0>;
40 d-cache-line-size = <32>; // 32 bytes
41 i-cache-line-size = <32>; // 32 bytes
42 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <0x8000>; // L1, 32K
44 next-level-cache = <&L2>;
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| D | tqm8548.dts | 13 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
34 #address-cells = <1>;
35 #size-cells = <0>;
40 d-cache-line-size = <32>; // 32 bytes
41 i-cache-line-size = <32>; // 32 bytes
42 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <0x8000>; // L1, 32K
44 next-level-cache = <&L2>;
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| D | stxssa8555.dts | 2 * MPC8555-based STx GP3 Device Tree Source
14 /dts-v1/;
18 compatible = "stx,gp3-8560", "stx,gp3";
19 #address-cells = <1>;
20 #size-cells = <1>;
31 #address-cells = <1>;
32 #size-cells = <0>;
37 d-cache-line-size = <32>; // 32 bytes
38 i-cache-line-size = <32>; // 32 bytes
39 d-cache-size = <0x8000>; // L1, 32K
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| D | mpc8541cds.dts | 12 /dts-v1/;
17 #address-cells = <1>;
18 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
40 timebase-frequency = <0>; // 33 MHz, from uboot
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| D | mpc8555cds.dts | 12 /dts-v1/;
17 #address-cells = <1>;
18 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
40 timebase-frequency = <0>; // 33 MHz, from uboot
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| D | mpc836x_rdk.dts | 5 * Copyright 2007-2008 MontaVista Software, Inc.
15 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
35 #address-cells = <1>;
36 #size-cells = <0>;
41 d-cache-line-size = <32>;
42 i-cache-line-size = <32>;
43 d-cache-size = <32768>;
44 i-cache-size = <32768>;
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| /linux-3.3/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | dma.txt | 7 - compatible : compatible list, contains 2 entries, first is
8 "fsl,CHIP-dma", where CHIP is the processor
10 "fsl,elo-dma"
11 - reg : <registers mapping for DMA general status reg>
12 - ranges : Should be defined as specified in 1) to describe the
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : <interrupt mapping for DMA IRQ>
16 - interrupt-parent : optional, if needed for interrupt mapping
19 - DMA channel nodes:
20 - compatible : compatible list, contains 2 entries, first is
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