Lines Matching +full:interrupt +full:- +full:parent
13 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
34 #address-cells = <1>;
35 #size-cells = <0>;
40 d-cache-line-size = <32>; // 32 bytes
41 i-cache-line-size = <32>; // 32 bytes
42 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <0x8000>; // L1, 32K
44 next-level-cache = <&L2>;
50 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
54 #address-cells = <1>;
55 #size-cells = <1>;
58 bus-frequency = <0>;
59 compatible = "fsl,mpc8548-immr", "simple-bus";
61 ecm-law@0 {
62 compatible = "fsl,ecm-law";
64 fsl,num-laws = <10>;
68 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
71 interrupt-parent = <&mpic>;
74 memory-controller@2000 {
75 compatible = "fsl,mpc8548-memory-controller";
77 interrupt-parent = <&mpic>;
81 L2: l2-cache-controller@20000 {
82 compatible = "fsl,mpc8548-l2-cache-controller";
84 cache-line-size = <32>; // 32 bytes
85 cache-size = <0x80000>; // L2, 512K
86 interrupt-parent = <&mpic>;
91 #address-cells = <1>;
92 #size-cells = <0>;
93 cell-index = <0>;
94 compatible = "fsl-i2c";
97 interrupt-parent = <&mpic>;
112 #address-cells = <1>;
113 #size-cells = <0>;
114 cell-index = <1>;
115 compatible = "fsl-i2c";
118 interrupt-parent = <&mpic>;
123 #address-cells = <1>;
124 #size-cells = <1>;
125 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
128 cell-index = <0>;
129 dma-channel@0 {
130 compatible = "fsl,mpc8548-dma-channel",
131 "fsl,eloplus-dma-channel";
133 cell-index = <0>;
134 interrupt-parent = <&mpic>;
137 dma-channel@80 {
138 compatible = "fsl,mpc8548-dma-channel",
139 "fsl,eloplus-dma-channel";
141 cell-index = <1>;
142 interrupt-parent = <&mpic>;
145 dma-channel@100 {
146 compatible = "fsl,mpc8548-dma-channel",
147 "fsl,eloplus-dma-channel";
149 cell-index = <2>;
150 interrupt-parent = <&mpic>;
153 dma-channel@180 {
154 compatible = "fsl,mpc8548-dma-channel",
155 "fsl,eloplus-dma-channel";
157 cell-index = <3>;
158 interrupt-parent = <&mpic>;
164 #address-cells = <1>;
165 #size-cells = <1>;
166 cell-index = <0>;
172 local-mac-address = [ 00 00 00 00 00 00 ];
174 interrupt-parent = <&mpic>;
175 tbi-handle = <&tbi0>;
176 phy-handle = <&phy2>;
179 #address-cells = <1>;
180 #size-cells = <0>;
181 compatible = "fsl,gianfar-mdio";
184 phy1: ethernet-phy@0 {
185 interrupt-parent = <&mpic>;
188 device_type = "ethernet-phy";
190 phy2: ethernet-phy@1 {
191 interrupt-parent = <&mpic>;
194 device_type = "ethernet-phy";
196 phy3: ethernet-phy@3 {
197 interrupt-parent = <&mpic>;
200 device_type = "ethernet-phy";
202 phy4: ethernet-phy@4 {
203 interrupt-parent = <&mpic>;
206 device_type = "ethernet-phy";
208 phy5: ethernet-phy@5 {
209 interrupt-parent = <&mpic>;
212 device_type = "ethernet-phy";
214 tbi0: tbi-phy@11 {
216 device_type = "tbi-phy";
222 #address-cells = <1>;
223 #size-cells = <1>;
224 cell-index = <1>;
230 local-mac-address = [ 00 00 00 00 00 00 ];
232 interrupt-parent = <&mpic>;
233 tbi-handle = <&tbi1>;
234 phy-handle = <&phy1>;
237 #address-cells = <1>;
238 #size-cells = <0>;
239 compatible = "fsl,gianfar-tbi";
242 tbi1: tbi-phy@11 {
244 device_type = "tbi-phy";
250 #address-cells = <1>;
251 #size-cells = <1>;
252 cell-index = <2>;
258 local-mac-address = [ 00 00 00 00 00 00 ];
260 interrupt-parent = <&mpic>;
261 tbi-handle = <&tbi2>;
262 phy-handle = <&phy4>;
265 #address-cells = <1>;
266 #size-cells = <0>;
267 compatible = "fsl,gianfar-tbi";
270 tbi2: tbi-phy@11 {
272 device_type = "tbi-phy";
278 #address-cells = <1>;
279 #size-cells = <1>;
280 cell-index = <3>;
286 local-mac-address = [ 00 00 00 00 00 00 ];
288 interrupt-parent = <&mpic>;
289 tbi-handle = <&tbi3>;
290 phy-handle = <&phy5>;
293 #address-cells = <1>;
294 #size-cells = <0>;
295 compatible = "fsl,gianfar-tbi";
298 tbi3: tbi-phy@11 {
300 device_type = "tbi-phy";
306 cell-index = <0>;
310 clock-frequency = <0>; // should we fill in in uboot?
311 current-speed = <115200>;
313 interrupt-parent = <&mpic>;
317 cell-index = <1>;
321 clock-frequency = <0>; // should we fill in in uboot?
322 current-speed = <115200>;
324 interrupt-parent = <&mpic>;
327 global-utilities@e0000 { // global utilities reg
328 compatible = "fsl,mpc8548-guts";
330 fsl,has-rstcr;
334 interrupt-controller;
335 #address-cells = <0>;
336 #interrupt-cells = <2>;
338 compatible = "chrp,open-pic";
339 device_type = "open-pic";
344 compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
345 "simple-bus";
346 #address-cells = <2>;
347 #size-cells = <1>;
349 interrupt-parent = <&mpic>;
361 #address-cells = <1>;
362 #size-cells = <1>;
363 compatible = "cfi-flash";
365 bank-width = <4>;
366 device-width = <1>;
389 label = "u-boot";
391 read-only;
395 /* Note: CAN support needs be enabled in U-Boot */
400 interrupt-parent = <&mpic>;
401 bosch,external-clock-frequency = <16000000>;
402 bosch,disconnect-rx1-input;
403 bosch,disconnect-tx1-output;
404 bosch,iso-low-speed-mux;
405 bosch,clock-out-frequency = <16000000>;
412 interrupt-parent = <&mpic>;
413 bosch,external-clock-frequency = <16000000>;
414 bosch,disconnect-rx1-input;
415 bosch,disconnect-tx1-output;
416 bosch,iso-low-speed-mux;
419 /* Note: NAND support needs to be enabled in U-Boot */
421 #address-cells = <0>;
422 #size-cells = <0>;
423 compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand";
425 fsl,upm-addr-offset = <0x10>;
426 fsl,upm-cmd-offset = <0x08>;
427 /* Micron MT29F8G08FAB multi-chip device */
428 fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
429 fsl,upm-wait-flags = <0x5>;
430 chip-delay = <25>; // in micro-seconds
433 #address-cells = <1>;
434 #size-cells = <1>;
445 #interrupt-cells = <1>;
446 #size-cells = <2>;
447 #address-cells = <3>;
448 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
451 clock-frequency = <33333333>;
452 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
453 interrupt-map = <
465 interrupt-parent = <&mpic>;
467 bus-range = <0 0>;
473 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
474 interrupt-map = <
481 interrupt-parent = <&mpic>;
483 bus-range = <0 0xff>;
486 clock-frequency = <33333333>;
487 #interrupt-cells = <1>;
488 #size-cells = <2>;
489 #address-cells = <3>;
491 compatible = "fsl,mpc8548-pcie";
495 #size-cells = <2>;
496 #address-cells = <3>;