boot/dts/mpc5121ads.dts

12 /dts-v1/;
17 	#address-cells = <1>;
18 	#size-cells = <1>;
25 		#address-cells = <1>;
26 		#size-cells = <0>;
31 			d-cache-line-size = <0x20>;	// 32 bytes
32 			i-cache-line-size = <0x20>;	// 32 bytes
33 			d-cache-size = <0x8000>;	// L1, 32K
34 			i-cache-size = <0x8000>;	// L1, 32K
35 			timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
36 			bus-frequency = <198000000>;	// 198 MHz csb bus
37 			clock-frequency = <396000000>;	// 396 MHz ppc core
47 		compatible = "fsl,mpc5121-mbx";
50 		interrupt-parent = < &ipic >;
54 		compatible = "fsl,mpc5121-sram";
59 		compatible = "fsl,mpc5121-nfc";
62 		interrupt-parent = < &ipic >;
63 		#address-cells = <1>;
64 		#size-cells = <1>;
75 		compatible = "fsl,mpc5121-localbus";
76 		#address-cells = <2>;
77 		#size-cells = <1>;
84 			compatible = "cfi-flash";
86 			#address-cells = <1>;
87 			#size-cells = <1>;
88 			bank-width = <4>;
89 			device-width = <2>;
93 				read-only;
103 			device-tree@3ec0000 {
104 				label = "device-tree";
107 			u-boot@3f00000 {
108 				label = "u-boot";
109 				reg = <0x03f00000 0x00100000>;  // 1M for u-boot
110 				read-only;
114 		board-control@2,0 {
115 			compatible = "fsl,mpc5121ads-cpld";
120 			compatible = "fsl,mpc5121ads-cpld-pic";
121 			interrupt-controller;
122 			#interrupt-cells = <2>;
124 			interrupt-parent = < &ipic >;
134 		compatible = "fsl,mpc5121-immr";
135 		#address-cells = <1>;
136 		#size-cells = <1>;
137 		#interrupt-cells = <2>;
140 		bus-frequency = <66000000>;	// 66 MHz ips bus
147 		// sense == 2: Edge, high-to-low change
149 		ipic: interrupt-controller@c00 {
150 			compatible = "fsl,mpc5121-ipic", "fsl,ipic";
151 			interrupt-controller;
152 			#address-cells = <0>;
153 			#interrupt-cells = <2>;
158 			compatible = "fsl,mpc5121-rtc";
161 			interrupt-parent = < &ipic >;
165 			compatible = "fsl,mpc5121-reset";
170 			compatible = "fsl,mpc5121-clock";
175 			compatible = "fsl,mpc5121-pmc";
178 			interrupt-parent = < &ipic >;
182 			compatible = "fsl,mpc5121-gpio";
185 			interrupt-parent = < &ipic >;
189 			compatible = "fsl,mpc5121-mscan";
191 			interrupt-parent = < &ipic >;
196 			compatible = "fsl,mpc5121-mscan";
198 			interrupt-parent = < &ipic >;
203 			#address-cells = <1>;
204 			#size-cells = <0>;
205 			compatible = "fsl,mpc5121-i2c", "fsl-i2c";
208 			interrupt-parent = < &ipic >;
209 			fsl,preserve-clocking;
228 			#address-cells = <1>;
229 			#size-cells = <0>;
230 			compatible = "fsl,mpc5121-i2c", "fsl-i2c";
233 			interrupt-parent = < &ipic >;
237 			#address-cells = <1>;
238 			#size-cells = <0>;
239 			compatible = "fsl,mpc5121-i2c", "fsl-i2c";
242 			interrupt-parent = < &ipic >;
246 			compatible = "fsl,mpc5121-i2c-ctrl";
251 			compatible = "fsl,mpc5121-axe";
254 			interrupt-parent = < &ipic >;
258 			compatible = "fsl,mpc5121-diu";
261 			interrupt-parent = < &ipic >;
265 			compatible = "fsl,mpc5121-fec-mdio";
267 			#address-cells = <1>;
268 			#size-cells = <0>;
269 			phy: ethernet-phy@0 {
271 				device_type = "ethernet-phy";
277 			compatible = "fsl,mpc5121-fec";
279 			local-mac-address = [ 00 00 00 00 00 00 ];
281 			interrupt-parent = < &ipic >;
282 			phy-handle = < &phy >;
283 			fsl,align-tx-packets = <4>;
291 		//	compatible = "fsl,mpc5121-usb2-dr";
293 		//	#address-cells = <1>;
294 		//	#size-cells = <0>;
295 		//	interrupt-parent = < &ipic >;
303 			compatible = "fsl,mpc5121-usb2-dr";
305 			#address-cells = <1>;
306 			#size-cells = <0>;
307 			interrupt-parent = < &ipic >;
311 			fsl,invert-drvvbus;
312 			fsl,invert-pwr-fault;
317 			compatible = "fsl,mpc5121-ioctl";
322 			compatible = "fsl,mpc5121-pata";
325 			interrupt-parent = < &ipic >;
332 			compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
335 			port-number = <0>;
336 			cell-index = <3>;
339 			interrupt-parent = < &ipic >;
340 			rx-fifo-size = <16>;
341 			tx-fifo-size = <16>;
347 			compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
350 			port-number = <1>;
351 			cell-index = <4>;
354 			interrupt-parent = < &ipic >;
355 			rx-fifo-size = <16>;
356 			tx-fifo-size = <16>;
361 			compatible = "fsl,mpc5121-psc-ac97", "fsl,mpc5121-psc";
362 			cell-index = <5>;
365 			interrupt-parent = < &ipic >;
366 			fsl,mode = "ac97-slave";
367 			rx-fifo-size = <384>;
368 			tx-fifo-size = <384>;
372 			compatible = "fsl,mpc5121-psc-fifo";
375 			interrupt-parent = < &ipic >;
379 			compatible = "fsl,mpc5121-dma";
382 			interrupt-parent = < &ipic >;
388 		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
389 		interrupt-map = <
390 				// IDSEL 0x15 - Slot 1 PCI
396 				// IDSEL 0x16 - Slot 2 MiniPCI
400 				// IDSEL 0x17 - Slot 3 MiniPCI
404 		interrupt-parent = < &ipic >;
406 		bus-range = <0 0>;
410 		clock-frequency = <0>;
411 		#interrupt-cells = <1>;
412 		#size-cells = <2>;
413 		#address-cells = <3>;
416 		compatible = "fsl,mpc5121-pci";