boot/dts/mpc8541cds.dts

12 /dts-v1/;
17 	#address-cells = <1>;
18 	#size-cells = <1>;
30 		#address-cells = <1>;
31 		#size-cells = <0>;
36 			d-cache-line-size = <32>;	// 32 bytes
37 			i-cache-line-size = <32>;	// 32 bytes
38 			d-cache-size = <0x8000>;		// L1, 32K
39 			i-cache-size = <0x8000>;		// L1, 32K
40 			timebase-frequency = <0>;	//  33 MHz, from uboot
41 			bus-frequency = <0>;	// 166 MHz
42 			clock-frequency = <0>;	// 825 MHz, from uboot
43 			next-level-cache = <&L2>;
53 		#address-cells = <1>;
54 		#size-cells = <1>;
56 		compatible = "simple-bus";
58 		bus-frequency = <0>;
60 		ecm-law@0 {
61 			compatible = "fsl,ecm-law";
63 			fsl,num-laws = <8>;
67 			compatible = "fsl,mpc8541-ecm", "fsl,ecm";
70 			interrupt-parent = <&mpic>;
73 		memory-controller@2000 {
74 			compatible = "fsl,mpc8541-memory-controller";
76 			interrupt-parent = <&mpic>;
80 		L2: l2-cache-controller@20000 {
81 			compatible = "fsl,mpc8541-l2-cache-controller";
83 			cache-line-size = <32>;	// 32 bytes
84 			cache-size = <0x40000>;	// L2, 256K
85 			interrupt-parent = <&mpic>;
90 			#address-cells = <1>;
91 			#size-cells = <0>;
92 			cell-index = <0>;
93 			compatible = "fsl-i2c";
96 			interrupt-parent = <&mpic>;
101 			#address-cells = <1>;
102 			#size-cells = <1>;
103 			compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma";
106 			cell-index = <0>;
107 			dma-channel@0 {
108 				compatible = "fsl,mpc8541-dma-channel",
109 						"fsl,eloplus-dma-channel";
111 				cell-index = <0>;
112 				interrupt-parent = <&mpic>;
115 			dma-channel@80 {
116 				compatible = "fsl,mpc8541-dma-channel",
117 						"fsl,eloplus-dma-channel";
119 				cell-index = <1>;
120 				interrupt-parent = <&mpic>;
123 			dma-channel@100 {
124 				compatible = "fsl,mpc8541-dma-channel",
125 						"fsl,eloplus-dma-channel";
127 				cell-index = <2>;
128 				interrupt-parent = <&mpic>;
131 			dma-channel@180 {
132 				compatible = "fsl,mpc8541-dma-channel",
133 						"fsl,eloplus-dma-channel";
135 				cell-index = <3>;
136 				interrupt-parent = <&mpic>;
142 			#address-cells = <1>;
143 			#size-cells = <1>;
144 			cell-index = <0>;
150 			local-mac-address = [ 00 00 00 00 00 00 ];
152 			interrupt-parent = <&mpic>;
153 			tbi-handle = <&tbi0>;
154 			phy-handle = <&phy0>;
157 				#address-cells = <1>;
158 				#size-cells = <0>;
159 				compatible = "fsl,gianfar-mdio";
162 				phy0: ethernet-phy@0 {
163 					interrupt-parent = <&mpic>;
166 					device_type = "ethernet-phy";
168 				phy1: ethernet-phy@1 {
169 					interrupt-parent = <&mpic>;
172 					device_type = "ethernet-phy";
174 				tbi0: tbi-phy@11 {
176 					device_type = "tbi-phy";
182 			#address-cells = <1>;
183 			#size-cells = <1>;
184 			cell-index = <1>;
190 			local-mac-address = [ 00 00 00 00 00 00 ];
192 			interrupt-parent = <&mpic>;
193 			tbi-handle = <&tbi1>;
194 			phy-handle = <&phy1>;
197 				#address-cells = <1>;
198 				#size-cells = <0>;
199 				compatible = "fsl,gianfar-tbi";
202 				tbi1: tbi-phy@11 {
204 					device_type = "tbi-phy";
210 			cell-index = <0>;
214 			clock-frequency = <0>; 	// should we fill in in uboot?
216 			interrupt-parent = <&mpic>;
220 			cell-index = <1>;
224 			clock-frequency = <0>; 	// should we fill in in uboot?
226 			interrupt-parent = <&mpic>;
233 			interrupt-parent = <&mpic>;
234 			fsl,num-channels = <4>;
235 			fsl,channel-fifo-len = <24>;
236 			fsl,exec-units-mask = <0x7e>;
237 			fsl,descriptor-types-mask = <0x01010ebf>;
241 			interrupt-controller;
242 			#address-cells = <0>;
243 			#interrupt-cells = <2>;
245 			compatible = "chrp,open-pic";
246 			device_type = "open-pic";
250 			#address-cells = <1>;
251 			#size-cells = <1>;
252 			compatible = "fsl,mpc8541-cpm", "fsl,cpm2";
257 				#address-cells = <1>;
258 				#size-cells = <1>;
262 					compatible = "fsl,cpm-muram-data";
268 				compatible = "fsl,mpc8541-brg",
269 				             "fsl,cpm2-brg",
270 				             "fsl,cpm-brg";
275 				interrupt-controller;
276 				#address-cells = <0>;
277 				#interrupt-cells = <2>;
279 				interrupt-parent = <&mpic>;
281 				compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
287 		interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
288 		interrupt-map = <
332 		interrupt-parent = <&mpic>;
334 		bus-range = <0 0>;
337 		clock-frequency = <66666666>;
338 		#interrupt-cells = <1>;
339 		#size-cells = <2>;
340 		#address-cells = <3>;
342 		compatible = "fsl,mpc8540-pci";
346 			interrupt-controller;
347 			device_type = "interrupt-controller";
349 			#address-cells = <0>;
350 			#interrupt-cells = <2>;
353 			interrupt-parent = <&pci0>;
358 		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
359 		interrupt-map = <
366 		interrupt-parent = <&mpic>;
368 		bus-range = <0 0>;
371 		clock-frequency = <66666666>;
372 		#interrupt-cells = <1>;
373 		#size-cells = <2>;
374 		#address-cells = <3>;
376 		compatible = "fsl,mpc8540-pci";