Lines Matching +full:interrupt +full:- +full:parent
13 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
36 d-cache-line-size = <32>;
37 i-cache-line-size = <32>;
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
40 timebase-frequency = <0>;
41 bus-frequency = <0>;
42 clock-frequency = <0>;
43 next-level-cache = <&L2>;
49 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 #address-cells = <1>;
54 #size-cells = <1>;
58 bus-frequency = <0>; // Filled in by U-Boot
59 compatible = "fsl,mpc8544-immr", "simple-bus";
61 ecm-law@0 {
62 compatible = "fsl,ecm-law";
64 fsl,num-laws = <10>;
68 compatible = "fsl,mpc8544-ecm", "fsl,ecm";
71 interrupt-parent = <&mpic>;
74 memory-controller@2000 {
75 compatible = "fsl,mpc8544-memory-controller";
77 interrupt-parent = <&mpic>;
81 L2: l2-cache-controller@20000 {
82 compatible = "fsl,mpc8544-l2-cache-controller";
84 cache-line-size = <32>;
85 cache-size = <0x40000>; // L2, 256K
86 interrupt-parent = <&mpic>;
91 #address-cells = <1>;
92 #size-cells = <0>;
93 cell-index = <0>;
94 compatible = "fsl,mpc8544-i2c", "fsl-i2c";
97 interrupt-parent = <&mpic>;
98 fsl,preserve-clocking;
108 interrupt-parent = <&mpic>;
117 interrupt-parent = <&mpic>;
123 #address-cells = <1>;
124 #size-cells = <0>;
125 cell-index = <1>;
126 compatible = "fsl,mpc8544-i2c", "fsl-i2c";
129 interrupt-parent = <&mpic>;
130 fsl,preserve-clocking;
134 #address-cells = <1>;
135 #size-cells = <1>;
136 cell-index = <0>;
142 local-mac-address = [ 00 00 00 00 00 00 ];
144 interrupt-parent = <&mpic>;
145 phy-handle = <&phy0>;
146 tbi-handle = <&tbi0>;
147 phy-connection-type = "rgmii-id";
150 #address-cells = <1>;
151 #size-cells = <0>;
152 compatible = "fsl,gianfar-mdio";
155 phy0: ethernet-phy@0 {
156 interrupt-parent = <&mpic>;
160 phy1: ethernet-phy@1 {
161 interrupt-parent = <&mpic>;
165 tbi0: tbi-phy@11 {
172 #address-cells = <1>;
173 #size-cells = <1>;
174 cell-index = <1>;
180 local-mac-address = [ 00 00 00 00 00 00 ];
182 interrupt-parent = <&mpic>;
183 phy-handle = <&phy1>;
184 tbi-handle = <&tbi1>;
185 phy-connection-type = "rgmii-id";
188 #address-cells = <1>;
189 #size-cells = <0>;
190 compatible = "fsl,gianfar-tbi";
193 tbi1: tbi-phy@11 {
200 cell-index = <0>;
204 clock-frequency = <0>;
206 interrupt-parent = <&mpic>;
210 cell-index = <1>;
214 clock-frequency = <0>;
216 interrupt-parent = <&mpic>;
219 global-utilities@e0000 { //global utilities block
220 compatible = "fsl,mpc8548-guts";
222 fsl,has-rstcr;
226 interrupt-controller;
227 #address-cells = <0>;
228 #interrupt-cells = <2>;
230 compatible = "chrp,open-pic";
231 device_type = "open-pic";
237 compatible = "fsl,mpc8544-localbus",
238 "fsl,pq3-localbus",
239 "simple-bus";
240 #address-cells = <2>;
241 #size-cells = <1>;
243 interrupt-parent = <&mpic>;
249 >; /* Overwritten by U-Boot */
252 compatible = "amd,s29gl256n", "cfi-flash";
253 bank-width = <2>;
255 #address-cells = <1>;
256 #size-cells = <1>;
260 read-only;
277 read-only;
280 label = "u-boot";
282 read-only;
289 interrupt-parent = <&mpic>;
293 fpga_pic: fpga-pic@3,10 {
294 compatible = "abb,socrates-fpga-pic";
296 interrupt-controller;
297 /* IRQs 2, 10, 11, active low, level-sensitive */
299 interrupt-parent = <&mpic>;
300 #interrupt-cells = <3>;
304 compatible = "abb,socrates-spi";
307 interrupt-parent = <&fpga_pic>;
311 compatible = "abb,socrates-nand";
313 bank-width = <1>;
314 #address-cells = <1>;
315 #size-cells = <1>;
326 interrupt-parent = <&fpga_pic>;
331 #interrupt-cells = <1>;
332 #size-cells = <2>;
333 #address-cells = <3>;
334 compatible = "fsl,mpc8540-pci";
337 clock-frequency = <66666666>;
339 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
340 interrupt-map = <
345 interrupt-parent = <&mpic>;
347 bus-range = <0x0 0x0>;