boot/dts/stxssa8555.dts

2  * MPC8555-based STx GP3 Device Tree Source
14 /dts-v1/;
18         compatible = "stx,gp3-8560", "stx,gp3";
19 	#address-cells = <1>;
20 	#size-cells = <1>;
31 		#address-cells = <1>;
32 		#size-cells = <0>;
37 			d-cache-line-size = <32>;	// 32 bytes
38 			i-cache-line-size = <32>;	// 32 bytes
39 			d-cache-size = <0x8000>;		// L1, 32K
40 			i-cache-size = <0x8000>;		// L1, 32K
41 			timebase-frequency = <0>;	//  33 MHz, from uboot
42 			bus-frequency = <0>;	// 166 MHz
43 			clock-frequency = <0>;	// 825 MHz, from uboot
44 			next-level-cache = <&L2>;
54 		#address-cells = <1>;
55 		#size-cells = <1>;
57 		compatible = "simple-bus";
59 		bus-frequency = <0>;
61 		ecm-law@0 {
62 			compatible = "fsl,ecm-law";
64 			fsl,num-laws = <8>;
68 			compatible = "fsl,mpc8555-ecm", "fsl,ecm";
71 			interrupt-parent = <&mpic>;
74 		memory-controller@2000 {
75 			compatible = "fsl,mpc8555-memory-controller";
77 			interrupt-parent = <&mpic>;
81 		L2: l2-cache-controller@20000 {
82 			compatible = "fsl,mpc8555-l2-cache-controller";
84 			cache-line-size = <32>;	// 32 bytes
85 			cache-size = <0x40000>;	// L2, 256K
86 			interrupt-parent = <&mpic>;
91 			#address-cells = <1>;
92 			#size-cells = <0>;
93 			cell-index = <0>;
94 			compatible = "fsl-i2c";
97 			interrupt-parent = <&mpic>;
102 			#address-cells = <1>;
103 			#size-cells = <1>;
104 			compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
107 			cell-index = <0>;
108 			dma-channel@0 {
109 				compatible = "fsl,mpc8555-dma-channel",
110 						"fsl,eloplus-dma-channel";
112 				cell-index = <0>;
113 				interrupt-parent = <&mpic>;
116 			dma-channel@80 {
117 				compatible = "fsl,mpc8555-dma-channel",
118 						"fsl,eloplus-dma-channel";
120 				cell-index = <1>;
121 				interrupt-parent = <&mpic>;
124 			dma-channel@100 {
125 				compatible = "fsl,mpc8555-dma-channel",
126 						"fsl,eloplus-dma-channel";
128 				cell-index = <2>;
129 				interrupt-parent = <&mpic>;
132 			dma-channel@180 {
133 				compatible = "fsl,mpc8555-dma-channel",
134 						"fsl,eloplus-dma-channel";
136 				cell-index = <3>;
137 				interrupt-parent = <&mpic>;
143 			#address-cells = <1>;
144 			#size-cells = <1>;
145 			cell-index = <0>;
151 			local-mac-address = [ 00 00 00 00 00 00 ];
153 			interrupt-parent = <&mpic>;
154 			tbi-handle = <&tbi0>;
155 			phy-handle = <&phy0>;
158 				#address-cells = <1>;
159 				#size-cells = <0>;
160 				compatible = "fsl,gianfar-mdio";
163 				phy0: ethernet-phy@2 {
164 					interrupt-parent = <&mpic>;
167 					device_type = "ethernet-phy";
169 				phy1: ethernet-phy@4 {
170 					interrupt-parent = <&mpic>;
173 					device_type = "ethernet-phy";
175 				tbi0: tbi-phy@11 {
177 					device_type = "tbi-phy";
183 			#address-cells = <1>;
184 			#size-cells = <1>;
185 			cell-index = <1>;
191 			local-mac-address = [ 00 00 00 00 00 00 ];
193 			interrupt-parent = <&mpic>;
194 			tbi-handle = <&tbi1>;
195 			phy-handle = <&phy1>;
198 				#address-cells = <1>;
199 				#size-cells = <0>;
200 				compatible = "fsl,gianfar-tbi";
203 				tbi1: tbi-phy@11 {
205 					device_type = "tbi-phy";
211 			cell-index = <0>;
215 			clock-frequency = <0>; 	// should we fill in in uboot?
217 			interrupt-parent = <&mpic>;
221 			cell-index = <1>;
225 			clock-frequency = <0>; 	// should we fill in in uboot?
227 			interrupt-parent = <&mpic>;
234 			interrupt-parent = <&mpic>;
235 			fsl,num-channels = <4>;
236 			fsl,channel-fifo-len = <24>;
237 			fsl,exec-units-mask = <0x7e>;
238 			fsl,descriptor-types-mask = <0x01010ebf>;
242 			interrupt-controller;
243 			#address-cells = <0>;
244 			#interrupt-cells = <2>;
246 			compatible = "chrp,open-pic";
247 			device_type = "open-pic";
251 			#address-cells = <1>;
252 			#size-cells = <1>;
253 			compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
258 				#address-cells = <1>;
259 				#size-cells = <1>;
263 					compatible = "fsl,cpm-muram-data";
269 				compatible = "fsl,mpc8555-brg",
270 				             "fsl,cpm2-brg",
271 				             "fsl,cpm-brg";
276 				interrupt-controller;
277 				#address-cells = <0>;
278 				#interrupt-cells = <2>;
280 				interrupt-parent = <&mpic>;
282 				compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
288 		interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
289 		interrupt-map = <
333 		interrupt-parent = <&mpic>;
335 		bus-range = <0 0>;
338 		clock-frequency = <66666666>;
339 		#interrupt-cells = <1>;
340 		#size-cells = <2>;
341 		#address-cells = <3>;
343 		compatible = "fsl,mpc8540-pci";
347 			interrupt-controller;
348 			device_type = "interrupt-controller";
350 			#address-cells = <0>;
351 			#interrupt-cells = <2>;
354 			interrupt-parent = <&pci0>;
359 		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
360 		interrupt-map = <
367 		interrupt-parent = <&mpic>;
369 		bus-range = <0 0>;
372 		clock-frequency = <66666666>;
373 		#interrupt-cells = <1>;
374 		#size-cells = <2>;
375 		#address-cells = <3>;
377 		compatible = "fsl,mpc8540-pci";