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/qemu/include/hw/ppc/
H A Dspapr_irq.h58 int (*activate)(SpaprInterruptController *intc, uint32_t nr_servers,
60 void (*deactivate)(SpaprInterruptController *intc);
66 int (*cpu_intc_create)(SpaprInterruptController *intc,
68 void (*cpu_intc_reset)(SpaprInterruptController *intc, PowerPCCPU *cpu);
69 void (*cpu_intc_destroy)(SpaprInterruptController *intc, PowerPCCPU *cpu);
70 int (*claim_irq)(SpaprInterruptController *intc, int irq, bool lsi,
72 void (*free_irq)(SpaprInterruptController *intc, int irq);
74 /* These methods should only be called on the active intc */
75 void (*set_irq)(SpaprInterruptController *intc, int irq, int val);
76 void (*print_info)(SpaprInterruptController *intc, GString *buf);
[all …]
H A Dxics_spapr.h38 int xics_kvm_connect(SpaprInterruptController *intc, uint32_t nr_servers,
40 void xics_kvm_disconnect(SpaprInterruptController *intc);
/qemu/hw/arm/
H A Daspeed_ast27x0-tsp.c121 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), in aspeed_soc_ast27x0tsp_get_irq()
145 object_initialize_child(obj, "intc0", &a->intc[0], in aspeed_soc_ast27x0tsp_init()
147 object_initialize_child(obj, "intc1", &a->intc[1], in aspeed_soc_ast27x0tsp_init()
200 /* INTC */ in aspeed_soc_ast27x0tsp_realize()
201 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) { in aspeed_soc_ast27x0tsp_realize()
205 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0, in aspeed_soc_ast27x0tsp_realize()
209 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) { in aspeed_soc_ast27x0tsp_realize()
213 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0, in aspeed_soc_ast27x0tsp_realize()
216 /* irq source orgates -> INTC */ in aspeed_soc_ast27x0tsp_realize()
217 for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_inpins; i++) { in aspeed_soc_ast27x0tsp_realize()
[all …]
H A Daspeed_ast27x0-ssp.c121 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), in aspeed_soc_ast27x0ssp_get_irq()
145 object_initialize_child(obj, "intc0", &a->intc[0], in aspeed_soc_ast27x0ssp_init()
147 object_initialize_child(obj, "intc1", &a->intc[1], in aspeed_soc_ast27x0ssp_init()
200 /* INTC */ in aspeed_soc_ast27x0ssp_realize()
201 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) { in aspeed_soc_ast27x0ssp_realize()
205 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0, in aspeed_soc_ast27x0ssp_realize()
209 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) { in aspeed_soc_ast27x0ssp_realize()
213 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0, in aspeed_soc_ast27x0ssp_realize()
217 for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_inpins; i++) { in aspeed_soc_ast27x0ssp_realize()
218 qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0, in aspeed_soc_ast27x0ssp_realize()
[all …]
H A Daspeed_ast27x0.c22 #include "hw/intc/arm_gicv3.h"
289 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), in aspeed_soc_ast2700_get_irq()
311 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), in aspeed_soc_ast2700_get_irq_index()
488 object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INTC); in aspeed_soc_ast2700_init()
489 object_initialize_child(obj, "intcio", &a->intc[1], in aspeed_soc_ast2700_init()
619 AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc[0]); in aspeed_soc_ast2700_realize()
620 AspeedINTCClass *icio = ASPEED_INTC_GET_CLASS(&a->intc[1]); in aspeed_soc_ast2700_realize()
650 /* INTC */ in aspeed_soc_ast2700_realize()
651 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) { in aspeed_soc_ast2700_realize()
655 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0, in aspeed_soc_ast2700_realize()
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H A Dallwinner-a10.c70 object_initialize_child(obj, "intc", &s->intc, TYPE_AW_A10_PIC); in aw_a10_init()
108 if (!sysbus_realize(SYS_BUS_DEVICE(&s->intc), errp)) { in aw_a10_realize()
111 sysbusdev = SYS_BUS_DEVICE(&s->intc); in aw_a10_realize()
117 qdev_pass_gpios(DEVICE(&s->intc), dev, NULL); in aw_a10_realize()
/qemu/hw/microblaze/
H A Dxlnx-zynqmp-pmu.c25 #include "hw/intc/xlnx-zynqmp-ipi.h"
26 #include "hw/intc/xlnx-pmu-iomod-intc.h"
55 XlnxPMUIOIntc intc; member
66 object_initialize_child(obj, "intc", &s->intc, TYPE_XLNX_PMU_IO_INTC); in xlnx_zynqmp_pmu_soc_init()
102 object_property_set_uint(OBJECT(&s->intc), "intc-intr-size", 0x10, in xlnx_zynqmp_pmu_soc_realize()
104 object_property_set_uint(OBJECT(&s->intc), "intc-level-edge", 0x0, in xlnx_zynqmp_pmu_soc_realize()
106 object_property_set_uint(OBJECT(&s->intc), "intc-positive", 0xffff, in xlnx_zynqmp_pmu_soc_realize()
108 if (!sysbus_realize(SYS_BUS_DEVICE(&s->intc), errp)) { in xlnx_zynqmp_pmu_soc_realize()
111 sysbus_mmio_map(SYS_BUS_DEVICE(&s->intc), 0, XLNX_ZYNQMP_PMU_INTC_ADDR); in xlnx_zynqmp_pmu_soc_realize()
112 sysbus_connect_irq(SYS_BUS_DEVICE(&s->intc), 0, in xlnx_zynqmp_pmu_soc_realize()
[all …]
/qemu/hw/intc/
H A Dxics_spapr.c310 static void xics_spapr_dt(SpaprInterruptController *intc, uint32_t nr_servers, in xics_spapr_dt() argument
332 static int xics_spapr_cpu_intc_create(SpaprInterruptController *intc, in xics_spapr_cpu_intc_create() argument
335 ICSState *ics = ICS_SPAPR(intc); in xics_spapr_cpu_intc_create()
348 static void xics_spapr_cpu_intc_reset(SpaprInterruptController *intc, in xics_spapr_cpu_intc_reset() argument
354 static void xics_spapr_cpu_intc_destroy(SpaprInterruptController *intc, in xics_spapr_cpu_intc_destroy() argument
363 static int xics_spapr_claim_irq(SpaprInterruptController *intc, int irq, in xics_spapr_claim_irq() argument
366 ICSState *ics = ICS_SPAPR(intc); in xics_spapr_claim_irq()
380 static void xics_spapr_free_irq(SpaprInterruptController *intc, int irq) in xics_spapr_free_irq() argument
382 ICSState *ics = ICS_SPAPR(intc); in xics_spapr_free_irq()
390 static void xics_spapr_set_irq(SpaprInterruptController *intc, int irq, int val) in xics_spapr_set_irq() argument
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H A Dloongarch_pch_msi.c11 #include "hw/intc/loongarch_pch_msi.h"
12 #include "hw/intc/loongarch_pch_pic.h"
40 * vector number is irq number from upper extioi intc in loongarch_msi_mem_write()
H A Dspapr_xive.c563 static int spapr_xive_post_load(SpaprInterruptController *intc, int version_id) in spapr_xive_post_load() argument
565 SpaprXive *xive = SPAPR_XIVE(intc); in spapr_xive_post_load()
590 static int spapr_xive_claim_irq(SpaprInterruptController *intc, int lisn, in spapr_xive_claim_irq() argument
593 SpaprXive *xive = SPAPR_XIVE(intc); in spapr_xive_claim_irq()
620 static void spapr_xive_free_irq(SpaprInterruptController *intc, int lisn) in spapr_xive_free_irq() argument
622 SpaprXive *xive = SPAPR_XIVE(intc); in spapr_xive_free_irq()
638 static int spapr_xive_cpu_intc_create(SpaprInterruptController *intc, in spapr_xive_cpu_intc_create() argument
641 SpaprXive *xive = SPAPR_XIVE(intc); in spapr_xive_cpu_intc_create()
660 static void spapr_xive_cpu_intc_reset(SpaprInterruptController *intc, in spapr_xive_cpu_intc_reset() argument
679 static void spapr_xive_cpu_intc_destroy(SpaprInterruptController *intc, in spapr_xive_cpu_intc_destroy() argument
[all …]
H A Dm68k_irqc.c15 #include "hw/intc/intc.h"
16 #include "hw/intc/m68k_irqc.h"
H A Daspeed_intc.c2 * ASPEED INTC Controller
10 #include "hw/intc/aspeed_intc.h"
18 * INTC Registers
66 * SSP INTC Registers
110 * TSP INTC Registers
810 object_initialize_child(obj, "intc-orgates[*]", &s->orgates[i], in aspeed_intc_instance_init()
873 dc->desc = "ASPEED INTC Controller"; in aspeed_intc_class_init()
910 dc->desc = "ASPEED 2700 INTC Controller"; in aspeed_2700_intc_class_init()
941 dc->desc = "ASPEED 2700 INTC IO Controller"; in aspeed_2700_intcio_class_init()
977 dc->desc = "ASPEED 2700 SSP INTC Controller"; in aspeed_2700ssp_intc_class_init()
[all …]
H A Dioapic_common.c26 #include "hw/intc/intc.h"
27 #include "hw/intc/ioapic.h"
28 #include "hw/intc/ioapic_internal.h"
H A Dintc.c26 #include "hw/intc/intc.h"
H A Domap_intc.c355 "omap-intc", s->size); in omap_intc_init()
364 error_setg(errp, "omap-intc: clk not connected"); in omap_intc_realize()
368 void omap_intc_set_iclk(OMAPIntcState *intc, omap_clk clk) in omap_intc_set_iclk() argument
370 intc->iclk = clk; in omap_intc_set_iclk()
373 void omap_intc_set_fclk(OMAPIntcState *intc, omap_clk clk) in omap_intc_set_fclk() argument
375 intc->fclk = clk; in omap_intc_set_fclk()
H A Dgoldfish_pic.c17 #include "hw/intc/intc.h"
18 #include "hw/intc/goldfish_pic.h"
/qemu/hw/ppc/
H A Dspapr_irq.c76 SpaprInterruptController *intc, in spapr_irq_init_kvm() argument
83 if (fn(intc, nr_servers, &local_err) < 0) { in spapr_irq_init_kvm()
218 SpaprInterruptController *intc = intcs[i]; in spapr_irq_cpu_intc_create() local
219 if (intc) { in spapr_irq_cpu_intc_create()
220 SpaprInterruptControllerClass *sicc = SPAPR_INTC_GET_CLASS(intc); in spapr_irq_cpu_intc_create()
221 rc = sicc->cpu_intc_create(intc, cpu, errp); in spapr_irq_cpu_intc_create()
237 SpaprInterruptController *intc = intcs[i]; in spapr_irq_cpu_intc_reset() local
238 if (intc) { in spapr_irq_cpu_intc_reset()
239 SpaprInterruptControllerClass *sicc = SPAPR_INTC_GET_CLASS(intc); in spapr_irq_cpu_intc_reset()
240 sicc->cpu_intc_reset(intc, cpu); in spapr_irq_cpu_intc_reset()
[all …]
/qemu/hw/sh4/
H A Dsh7750.c81 struct intc_desc intc; member
755 sh_intc_init(sysmem, &s->intc, NR_SOURCES, in sh7750_init()
759 sh_intc_register_sources(&s->intc, in sh7750_init()
763 cpu->env.intc_handle = &s->intc; in sh7750_init()
777 qdev_connect_gpio_out_named(dev, "eri", 0, s->intc.irqs[SCI1_ERI]); in sh7750_init()
778 qdev_connect_gpio_out_named(dev, "rxi", 0, s->intc.irqs[SCI1_RXI]); in sh7750_init()
779 qdev_connect_gpio_out_named(dev, "txi", 0, s->intc.irqs[SCI1_TXI]); in sh7750_init()
780 qdev_connect_gpio_out_named(dev, "tei", 0, s->intc.irqs[SCI1_TEI]); in sh7750_init()
795 qdev_connect_gpio_out_named(dev, "eri", 0, s->intc.irqs[SCIF_ERI]); in sh7750_init()
796 qdev_connect_gpio_out_named(dev, "rxi", 0, s->intc.irqs[SCIF_RXI]); in sh7750_init()
[all …]
/qemu/include/hw/arm/
H A Daspeed_soc.h17 #include "hw/intc/aspeed_vic.h"
18 #include "hw/intc/aspeed_intc.h"
43 #include "hw/intc/arm_gicv3.h"
135 AspeedINTCState intc[2]; member
151 AspeedINTCState intc[2]; member
163 AspeedINTCState intc[2]; member
H A Dallwinner-a10.h5 #include "hw/intc/allwinner-a10-pic.h"
39 AwA10PICState intc; member
/qemu/docs/specs/
H A Daspeed-intc.rst11 There are two levels of interrupt controllers, INTC (CPU Die) and INTCIO
16 - INTC: Handles interrupt sources 0 - 127 and integrates signals from INTCIO.
22 from INTCIO and connected to INTC at input pin 0 and output pins 0 to 9 for
28 connected to INTCIO "T0 GICINT_196". The output pin is then connected to INTC
31 INTC GIC_192_201 Output Pin Mapping
33 The design of INTC GIC_192_201 have 10 output pins, mapped as following:
52 It has only one INTC controller, and currently, only GIC 128-136 is supported.
53 To support both AST2700 A1 and AST2700 A0, there are 10 OR gates in the INTC,
59 connected to INTC. The output pin is then connected to GIC 132.
91 …| -------->|14 | | | INTC | | GI…
/qemu/hw/core/
H A Dmachine-qmp-cmds.c13 #include "hw/intc/intc.h"
326 InterruptStatsProvider *intc; in qmp_x_query_irq_foreach() local
331 intc = INTERRUPT_STATS_PROVIDER(obj); in qmp_x_query_irq_foreach()
336 k->get_statistics(intc, &irq_counts, &nb_irqs)) { in qmp_x_query_irq_foreach()
369 InterruptStatsProvider *intc; in qmp_x_query_intc_foreach() local
374 intc = INTERRUPT_STATS_PROVIDER(obj); in qmp_x_query_intc_foreach()
377 k->print_info(intc, buf); in qmp_x_query_intc_foreach()
/qemu/include/hw/isa/
H A Di8259_internal.h29 #include "hw/intc/intc.h"
30 #include "hw/intc/i8259.h"
/qemu/include/hw/intc/
H A Daspeed_intc.h2 * ASPEED INTC Controller
15 #define TYPE_ASPEED_INTC "aspeed.intc"
/qemu/pc-bios/dtb/
H A Dpetalogix-ml605.dts144 interrupt-parent = < &intc >;
182 interrupt-parent = < &intc >;
205 interrupt-parent = < &intc >;
222 interrupt-parent = < &intc >;
234 intc: interrupt-controller@81800000 { label
236 compatible = "xlnx,axi-intc-1.01.a\0xlnx,xps-intc-1.00.a";

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