1=========================== 2ASPEED Interrupt Controller 3=========================== 4 5AST2700 6------- 7There are a total of 480 interrupt sources in AST2700. Due to the limitation of 8interrupt numbers of processors, the interrupts are merged every 32 sources for 9interrupt numbers greater than 127. 10 11There are two levels of interrupt controllers, INTC (CPU Die) and INTCIO 12(I/O Die). 13 14Interrupt Mapping 15----------------- 16- INTC: Handles interrupt sources 0 - 127 and integrates signals from INTCIO. 17- INTCIO: Handles interrupt sources 128 - 319 independently. 18 19QEMU Support 20------------ 21Currently, only GIC 192 to 201 are supported, and their source interrupts are 22from INTCIO and connected to INTC at input pin 0 and output pins 0 to 9 for 23GIC 192-201. 24 25Design for GICINT 196 26--------------------- 27The orgate has interrupt sources ranging from 0 to 31, with its output pin 28connected to INTCIO "T0 GICINT_196". The output pin is then connected to INTC 29"GIC_192_201" at bit 4, and its bit 4 output pin is connected to GIC 196. 30 31INTC GIC_192_201 Output Pin Mapping 32----------------------------------- 33The design of INTC GIC_192_201 have 10 output pins, mapped as following: 34 35==== ==== 36Bit GIC 37==== ==== 380 192 391 193 402 194 413 195 424 196 435 197 446 198 457 199 468 200 479 201 48==== ==== 49 50AST2700 A0 51---------- 52It has only one INTC controller, and currently, only GIC 128-136 is supported. 53To support both AST2700 A1 and AST2700 A0, there are 10 OR gates in the INTC, 54with gates 1 to 9 supporting GIC 128-136. 55 56Design for GICINT 132 57--------------------- 58The orgate has interrupt sources ranging from 0 to 31, with its output pin 59connected to INTC. The output pin is then connected to GIC 132. 60 61Block Diagram of GICINT 196 for AST2700 A1 and GICINT 132 for AST2700 A0 62------------------------------------------------------------------------ 63 64.. code-block:: 65 66 |-------------------------------------------------------------------------------------------------------| 67 | AST2700 A1 Design | 68 | To GICINT196 | 69 | | 70 | ETH1 |-----------| |--------------------------| |--------------| | 71 | -------->|0 | | INTCIO | | orgates[0] | | 72 | ETH2 | 4| orgates[0]------>|inpin[0]-------->outpin[0]|------->| 0 | | 73 | -------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1]|------->| 1 | | 74 | ETH3 | 6| orgates[2]------>|inpin[2]-------->outpin[2]|------->| 2 | | 75 | -------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3]|------->| 3 OR[0:9] |-----| | 76 | UART0 | 20|-->orgates[4]------>|inpin[4]-------->outpin[4]|------->| 4 | | | 77 | -------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5]|------->| 5 | | | 78 | UART1 | 22| orgates[6]------>|inpin[6]-------->outpin[6]|------->| 6 | | | 79 | -------->|8 23| orgates[7]------>|inpin[7]-------->outpin[7]|------->| 7 | | | 80 | UART2 | 24| orgates[8]------>|inpin[8]-------->outpin[8]|------->| 8 | | | 81 | -------->|9 25| orgates[9]------>|inpin[9]-------->outpin[9]|------->| 9 | | | 82 | UART3 | 26| |--------------------------| |--------------| | | 83 | ---------|10 27| | | 84 | UART5 | 28| | | 85 | -------->|11 29| | | 86 | UART6 | | | | 87 | -------->|12 30| |-----------------------------------------------------------------------| | 88 | UART7 | 31| | | 89 | -------->|13 | | | 90 | UART8 | OR[0:31] | | |------------------------------| |----------| | 91 | -------->|14 | | | INTC | | GIC | | 92 | UART9 | | | |inpin[0:0]--------->outpin[0] |---------->|192 | | 93 | -------->|15 | | |inpin[0:1]--------->outpin[1] |---------->|193 | | 94 | UART10 | | | |inpin[0:2]--------->outpin[2] |---------->|194 | | 95 | -------->|16 | | |inpin[0:3]--------->outpin[3] |---------->|195 | | 96 | UART11 | | |--------------> |inpin[0:4]--------->outpin[4] |---------->|196 | | 97 | -------->|17 | |inpin[0:5]--------->outpin[5] |---------->|197 | | 98 | UART12 | | |inpin[0:6]--------->outpin[6] |---------->|198 | | 99 | -------->|18 | |inpin[0:7]--------->outpin[7] |---------->|199 | | 100 | |-----------| |inpin[0:8]--------->outpin[8] |---------->|200 | | 101 | |inpin[0:9]--------->outpin[9] |---------->|201 | | 102 |-------------------------------------------------------------------------------------------------------| 103 |-------------------------------------------------------------------------------------------------------| 104 | ETH1 |-----------| orgates[1]------->|inpin[1]----------->outpin[10]|---------->|128 | | 105 | -------->|0 | orgates[2]------->|inpin[2]----------->outpin[11]|---------->|129 | | 106 | ETH2 | 4| orgates[3]------->|inpin[3]----------->outpin[12]|---------->|130 | | 107 | -------->|1 5| orgates[4]------->|inpin[4]----------->outpin[13]|---------->|131 | | 108 | ETH3 | 6|---->orgates[5]------->|inpin[5]----------->outpin[14]|---------->|132 | | 109 | -------->|2 19| orgates[6]------->|inpin[6]----------->outpin[15]|---------->|133 | | 110 | UART0 | 20| orgates[7]------->|inpin[7]----------->outpin[16]|---------->|134 | | 111 | -------->|7 21| orgates[8]------->|inpin[8]----------->outpin[17]|---------->|135 | | 112 | UART1 | 22| orgates[9]------->|inpin[9]----------->outpin[18]|---------->|136 | | 113 | -------->|8 23| |------------------------------| |----------| | 114 | UART2 | 24| | 115 | -------->|9 25| AST2700 A0 Design | 116 | UART3 | 26| | 117 | -------->|10 27| | 118 | UART5 | 28| | 119 | -------->|11 29| GICINT132 | 120 | UART6 | | | 121 | -------->|12 30| | 122 | UART7 | 31| | 123 | -------->|13 | | 124 | UART8 | OR[0:31] | | 125 | -------->|14 | | 126 | UART9 | | | 127 | -------->|15 | | 128 | UART10 | | | 129 | -------->|16 | | 130 | UART11 | | | 131 | -------->|17 | | 132 | UART12 | | | 133 | -------->|18 | | 134 | |-----------| | 135 | | 136 |-------------------------------------------------------------------------------------------------------| 137