1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * QEMU Loongson 7A1000 msi interrupt controller.
4 *
5 * Copyright (C) 2021 Loongson Technology Corporation Limited
6 */
7
8 #include "qemu/osdep.h"
9 #include "hw/sysbus.h"
10 #include "hw/irq.h"
11 #include "hw/intc/loongarch_pch_msi.h"
12 #include "hw/intc/loongarch_pch_pic.h"
13 #include "hw/pci/msi.h"
14 #include "hw/misc/unimp.h"
15 #include "migration/vmstate.h"
16 #include "trace.h"
17
loongarch_msi_mem_read(void * opaque,hwaddr addr,unsigned size)18 static uint64_t loongarch_msi_mem_read(void *opaque, hwaddr addr, unsigned size)
19 {
20 return 0;
21 }
22
loongarch_msi_mem_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)23 static void loongarch_msi_mem_write(void *opaque, hwaddr addr,
24 uint64_t val, unsigned size)
25 {
26 LoongArchPCHMSI *s = (LoongArchPCHMSI *)opaque;
27 int irq_num;
28
29 /*
30 * vector number is irq number from upper extioi intc
31 * need subtract irq base to get msi vector offset
32 */
33 irq_num = (val & 0xff) - s->irq_base;
34 trace_loongarch_msi_set_irq(irq_num);
35 assert(irq_num < s->irq_num);
36 qemu_set_irq(s->pch_msi_irq[irq_num], 1);
37 }
38
39 static const MemoryRegionOps loongarch_pch_msi_ops = {
40 .read = loongarch_msi_mem_read,
41 .write = loongarch_msi_mem_write,
42 .endianness = DEVICE_LITTLE_ENDIAN,
43 };
44
loongarch_pch_msi_realize(DeviceState * dev,Error ** errp)45 static void loongarch_pch_msi_realize(DeviceState *dev, Error **errp)
46 {
47 LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(dev);
48
49 if (!s->irq_num || s->irq_num > PCH_MSI_IRQ_NUM) {
50 error_setg(errp, "Invalid 'msi_irq_num'");
51 return;
52 }
53
54 s->pch_msi_irq = g_new(qemu_irq, s->irq_num);
55 qdev_init_gpio_out(dev, s->pch_msi_irq, s->irq_num);
56 }
57
loongarch_pch_msi_unrealize(DeviceState * dev)58 static void loongarch_pch_msi_unrealize(DeviceState *dev)
59 {
60 LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(dev);
61
62 g_free(s->pch_msi_irq);
63 }
64
loongarch_pch_msi_init(Object * obj)65 static void loongarch_pch_msi_init(Object *obj)
66 {
67 LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(obj);
68 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
69
70 memory_region_init_io(&s->msi_mmio, obj, &loongarch_pch_msi_ops,
71 s, TYPE_LOONGARCH_PCH_MSI, 0x8);
72 sysbus_init_mmio(sbd, &s->msi_mmio);
73 msi_nonbroken = true;
74
75 }
76
77 static const Property loongarch_msi_properties[] = {
78 DEFINE_PROP_UINT32("msi_irq_base", LoongArchPCHMSI, irq_base, 0),
79 DEFINE_PROP_UINT32("msi_irq_num", LoongArchPCHMSI, irq_num, 0),
80 };
81
loongarch_pch_msi_class_init(ObjectClass * klass,const void * data)82 static void loongarch_pch_msi_class_init(ObjectClass *klass, const void *data)
83 {
84 DeviceClass *dc = DEVICE_CLASS(klass);
85
86 dc->realize = loongarch_pch_msi_realize;
87 dc->unrealize = loongarch_pch_msi_unrealize;
88 device_class_set_props(dc, loongarch_msi_properties);
89 }
90
91 static const TypeInfo loongarch_pch_msi_info = {
92 .name = TYPE_LOONGARCH_PCH_MSI,
93 .parent = TYPE_SYS_BUS_DEVICE,
94 .instance_size = sizeof(LoongArchPCHMSI),
95 .instance_init = loongarch_pch_msi_init,
96 .class_init = loongarch_pch_msi_class_init,
97 };
98
loongarch_pch_msi_register_types(void)99 static void loongarch_pch_msi_register_types(void)
100 {
101 type_register_static(&loongarch_pch_msi_info);
102 }
103
104 type_init(loongarch_pch_msi_register_types)
105